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PDF 54F193 Data sheet ( Hoja de datos )
| Número de pieza | 54F193 | |
| Descripción | Up/Down Binary Counter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
November 1994
54F 74F193 Up Down Binary Counter
with Separate Up Down Clocks
General Description
The ’F193 is an up down modulo-16 binary counter Sepa-
rate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs Separate Terminal
Count Up and Terminal Count Down outputs are provided
that are used as the clocks for subsequent stages without
extra logic thus simplifying multi-stage counter designs
Individual preset inputs allow the circuit to be used as a
programmable counter Both the Parallel Load (PL) and the
Master Reset (MR) inputs asynchronously override the
clocks
Features
Y Guaranteed 4000V minimum ESD protection
Commercial
74F193PC
74F193SC (Note 1)
74F193SJ (Note 1)
Military
54F193DM (Note 2)
54F193FM (Note 2)
54F193LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
IEEE IEC
TL F 9497–1
TL F 9497 – 2
TL F 9497 – 3
TL F 9497–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9497
RRD-B30M75 Printed in U S A
1 page  
AC Electrical Characteristics
Symbol
Parameter
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Maximum Count Frequency
Propagation Delay
CPU or CPD to
TCU or TCD
Propagation Delay
CPU or CPD to Qn
Propagation Delay
Pn to Qn
Propagation Delay
PL to Qn
Propagation Delay
MR to Qn
Propagation Delay
MR to TCU
Propagation Delay
MR to TCD
Propagation Delay
PL to TCU or TCD
Propagation Delay
Pn to TCU or TCD
74F
TA e a25 C
VCC e a5 0V
CL e 50 pF
Min Typ Max
100 125
40 70 90
35 60 80
40 65 85
5 5 9 5 12 5
30 45 70
6 0 11 0 14 5
5 0 8 5 11 0
5 5 10 0 13 0
5 5 11 0 14 5
6 0 10 5 13 5
6 0 11 5 14 5
7 0 12 0 15 5
7 0 11 5 14 5
7 0 11 5 14 5
6 5 11 0 14 0
54F
TA VCC e Mil
CL e 50 pF
Min Max
75
4 0 10 5
35 95
3 5 10 0
5 5 14 0
30 85
6 0 16 5
5 0 13 5
5 5 15 0
5 0 16 0
5 0 15 0
6 0 16 0
7 0 18 5
6 0 17 5
6 0 16 5
5 0 16 5
AC Operating Requirements
Symbol
Parameter
ts(H)
ts(L)
th(H)
th(L)
tw(L)
tw(L)
tw(L)
tw(H)
trec
trec
Setup Time HIGH or LOW
Pn to PL
Hold Time HIGH or LOW
Pn to PL
PL Pulse Width LOW
CPU or CPD
Pulse Width LOW
CPU or CPD
Pulse Width LOW
(Change of Direction)
MR Pulse Width HIGH
Recovery Time
PL to CPU or CPD
Recovery Time
MR to CPU or CPD
74F
TA e a25 C
VCC e a5 0V
Min Max
45
45
20
20
60
50
10 0
60
60
40
54F
TA VCC e Mil
Min Max
60
60
20
20
75
70
12 0
60
80
45
74F
TA VCC e Com
CL e 50 pF
Min Max
90
4 0 10 0
35 90
40 95
5 5 13 5
30 80
6 0 15 5
5 0 12 0
5 5 14 0
5 5 15 5
6 0 14 5
6 0 15 5
7 0 16 5
7 0 15 5
7 0 15 5
6 5 15 0
74F
TA VCC e Com
Min Max
50
50
20
20
60
50
10 0
60
60
40
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 54F193.PDF ] | |
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