PDF MT18LD272A Data sheet ( Hoja de datos )

Número de pieza	MT18LD272A
Descripción	(MT18LD272A / MT18LD472A) NONBUFFERED DRAM DIMMs
Fabricantes	Micron Technology
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No Preview Available ! www.DataSheet4U.com OBSOLETE 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs DRAM MODULE MT9LD272A(X), MT18LD472A(X) For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES • JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin, dual in-line memory module (DIMM) • 16MB (2 Meg x 72) and 32MB (4 Meg x 72) • Nonbuffered • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • 2,048-cycle refresh distributed across 32ms • FAST-PAGE-MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles • Serial presence-detect (SPD) OPTIONS • Package 168-pin DIMM (gold) • Timing 50ns access 60ns access • Access Cycles FAST PAGE MODE EDO PAGE MODE EDO version only MARKING G -5 -6 None X KEY TIMING PARAMETERS EDO Operating Mode SPEED -5 -6 tRC 84ns 104ns tRAC 50ns 60ns tPC 20ns 25ns tAA 25ns 30ns tCAC 13ns 15ns tCAS 8ns 10ns FPM Operating Mode SPEED tRC tRAC -6 110ns 60ns tPC 35ns tAA 30ns tCAC 15ns tRP 40ns NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. 2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 – Rev. 6/98 1 PIN ASSIGNMENT (Front View) 168-Pin DIMM PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 OE2# 86 DQ32 128 RFU 3 DQ1 45 RAS2# 87 DQ33 129 NC/RAS3#* 4 DQ2 46 CAS2# 88 DQ34 130 CAS6# 5 DQ3 47 CAS3# 89 DQ35 131 CAS7# 6 VDD 48 WE2# 90 VDD 132 RFU 7 DQ4 49 VDD 91 DQ36 133 VDD 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 RFU 104 DQ47 146 RFU 21 CB0 63 NC 105 CB4 147 NC 22 CB1 64 VSS 106 CB5 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 VDD 68 VSS 110 VDD 152 VSS 27 WE0# 69 DQ24 111 RFU 153 DQ56 28 CAS0# 70 DQ25 112 CAS4# 154 DQ57 29 CAS1# 71 DQ26 113 CAS5# 155 DQ58 30 RAS0# 72 DQ27 114 NC 156 DQ59 31 OE0# 73 VDD 115 RFU 157 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 NC 121 A9 163 NC 38 A10 80 NC 122 NC (A11) 164 NC 39 NC (A12) 81 NC 123 NC (A13) 165 SA0 40 VDD 82 SDA 124 VDD 166 SA1 41 VDD 83 SCL 125 RFU 167 SA2 42 RFU 84 VDD 126 RFU 168 VDD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. 1 page OBSOLETE 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3# A0-A10 WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7# FUNCTIONAL BLOCK DIAGRAM MT18LD472A(X) (32MB) DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 CB4-CB7 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ0-DQ3 WE# OE# U1 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U2 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U3 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U4 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U5 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U6 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U7 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U8 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U9 RAS# CAS# A0–A10 11 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 CB4-CB7 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ06-DQ63 DQ0-DQ3 WE# OE# U10 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U11 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U12 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U13 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U14 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U15 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U16 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U17 RAS# CAS# A0–A10 11 DQ0-DQ3 WE# OE# U18 RAS# CAS# A0–A10 11 SCL SPD A0 A1 A2 SA0 SA1 SA2 SDA VDD VSS U1-U18 U1-U18 U1-U18 = MT4LC4M4B1 FAST PAGE MODE U1-U18 = MT4LC4M4E8 EDO PAGE MODE 2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 – Rev. 6/98 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. 5 Page OBSOLETE FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs SYMBOL tPRWC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP -6 MIN MAX 85 60 15 10 60 10,000 60 125,000 110 20 0 0 32 40 0 0 15 155 85 15 2 50 10 45 0 10 10 10 UNITS ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 13 17 16 18 18 23 23 2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 – Rev. 6/98 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. 11 Page

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