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SC18IS601 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 SC18IS601은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 SC18IS601 기능
기능 (SC18IS600 / SC18IS601) SPI to IC-bus interface
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SC18IS601 데이터시트, 핀배열, 회로
www.DataSheet4U.com
SC18IS600/601
SPI to I2C-bus interface
Rev. 03 — 13 December 2006
Product data sheet
1. General description
The SC18IS600/601 is designed to serve as an interface between the standard SPI of a
host (microcontroller, microprocessor, chip set, etc.) and the serial I2C-bus. This allows
the host to communicate directly with other I2C-bus devices. The SC18IS600/601 can
operate as an I2C-bus master-transmitter or master-receiver. The SC18IS600/601
controls all the I2C-bus specific sequences, protocol, arbitration and timing.
The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source:
internal (SC18IS600) versus external (SC18IS601).
2. Features
I SPI slave interface
I SPI Mode 3
I Master I2C-bus controller
I General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601)
I Two quasi-bidirectional I/O pins
I 5 V tolerant I/O pins
I High-speed SPI:
N Up to 3 Mbit/s (SC18IS601)
N Up to 1.2 Mbit/s (SC18IS600)
I High-speed I2C-bus: 400 kbit/s
I 96-byte transmit buffer
I 96-byte receive buffer
I 2.4 V to 3.6 V operation
I Power-down mode with WAKEUP pin
I Oscillator: internal (SC18IS600); external (SC18IS601)
I Active LOW interrupt output
I Available in very small TSSOP16 package
3. Ordering information
Table 1. Ordering information
Type number Package
Name
Description
SC18IS600IPW TSSOP16 plastic thin shrink small outline package; 16 leads;
SC18IS601IPW
body width 4.4 mm
Version
SOT403-1




SC18IS601 pdf, 반도체, 판매, 대치품
NXP Semiconductors
5. Pinning information
5.1 Pinning
SC18IS600/601
SPI to I2C-bus interface
GPIO0 1
CS 2
RESET 3
VSS 4
MISO 5
MOSI 6
SDA 7
SCL 8
SC18IS600IPW
16 IO5
15 WAKEUP/IO4
14 INT
13 GPIO3
12 VDD
11 SCLK
10 GPIO2
9 GPIO1
002aab713
Fig 3. SC18IS600 pin configuration for TSSOP16
GPIO0 1
CS 2
RESET 3
VSS 4
MISO 5
MOSI 6
SDA 7
SCL 8
SC18IS601IPW
16 IO5
15 WAKEUP/IO4
14 INT
13 CLKIN
12 VDD
11 SCLK
10 GPIO2
9 GPIO1
002aab714
Fig 4. SC18IS601 pin configuration for TSSOP16
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Type Description
SC18IS600 SC18IS601
GPIO0
1
1
I/O programmable I/O pin
CS 2 2 I Chip select. When CS is LOW, the SC18IS600/601 is selected.
RESET
3
3
I Master Reset. When active (LOW), RESET sets internal registers to
the default values, and resets the I2C-bus and SPI hardware. See
Table 3.
VSS 4 4 I ground supply voltage
MISO
5
5
O SPI slave data output
MOSI
6
6
I SPI slave data input
SDA 7 7 I/O I2C-bus serial data input/output
SCL
8 8 O I2C-bus serial clock output
GPIO1
9
9
I/O programmable I/O pin
GPIO2
10
10
I/O programmable I/O pin
SCLK 11 11 I SPI clock input
VDD 12 12 I 2.4 V to 3.6 V supply voltage
GPIO3
13
-
I/O programmable I/O pin
CLKIN
-
13 I external clock input
INT 14 14 O Interrupt. When active (LOW), INT informs the CPU that the
SC18IS600/601 has an interrupt to be serviced.
INT is reset (deactivated) either when the I2CStat register is read or as
a result of a master reset (RESET). This pin is an open-drain pin.
WAKEUP/IO4 15 15 I/O Wake up the SC18IS600/601 from the Power-down mode. Pulled LOW
by the host to wake-up from low power state. This pin can also be used
as a quasi-bidirectional I/O when not in a power-down state.
IO5 16 16 I/O quasi-bidirectional I/O pin
SC18IS600_601_3
Product data sheet
Rev. 03 — 13 December 2006
© NXP B.V. 2006. All rights reserved.
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SC18IS601 전자부품, 판매, 대치품
NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
6.2.1.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the pin when the pin latch contains a logic 0. To be used as a logic output, a
pin configured in this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.
The open-drain pin configuration is shown in Figure 6.
An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
pin latch data
VSS
input data
Fig 6. Open-drain output configuration
GPIO pin
glitch rejection
002aab883
6.2.1.3 Input-only configuration
The input-only pin configuration is shown in Figure 7. It is a Schmitt-triggered input that
also has a glitch suppression circuit.
input data
Fig 7. Input-only configuration
GPIO pin
glitch rejection
002aab884
6.2.1.4 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the pin latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a pin output.
The push-pull pin configuration is shown in Figure 8.
A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.
SC18IS600_601_3
Product data sheet
Rev. 03 — 13 December 2006
© NXP B.V. 2006. All rights reserved.
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(SC18IS600 / SC18IS601) SPI to IC-bus interface

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SC18IS601

(SC18IS600 / SC18IS601) SPI to IC-bus interface

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