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UC1861 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 UC1861
기능 (UC1861 - 1868) Resonant-Mode Power Supply Controllers
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UC1861 데이터시트, 핀배열, 회로
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Resonant-Mode Power Supply Controllers
UC1861-1868
UC2861-2868
UC3861-3868
FEATURES
DESCRIPTION
Controls Zero Current Switched (ZCS)
or Zero Voltage Switched (ZVS)
Quasi-Resonant Converters
Zero-Crossing Terminated One-Shot
Timer
Precision 1%, Soft-Started 5V
Reference
Programmable Restart Delay
Following Fault
Voltage-Controlled Oscillator (VCO)
with Programmable Minimum and
Maximum Frequencies from 10kHz to
1MHz
Low Start-Up Current (150µA typical)
Dual 1 Amp Peak FET Drivers
UVLO Option for Off-Line or DC/DC
Applications
The UC1861-1868 family of ICs is optimized for the control of Zero Cur-
rent Switched and Zero Voltage Switched quasi-resonant converters. Dif-
ferences between members of this device family result from the various
combinations of UVLO thresholds and output options. Additionally, the
one-shot pulse steering logic is configured to program either on-time for
ZCS systems (UC1865-1868), or off-time for ZVS applications (UC1861-
1864).
The primary control blocks implemented include an error amplifier to com-
pensate the overall system loop and to drive a voltage controlled oscillator
(VCO), featuring programmable minimum and maximum frequencies. Trig-
gered by the VCO, the one-shot generates pulses of a programmed maxi-
mum width, which can be modulated by the Zero Detection comparator.
This circuit facilitates “true” zero current or voltage switching over various
line, load, and temperature changes, and is also able to accommodate the
resonant components' initial tolerances.
Under-Voltage Lockout is incorporated to facilitate safe starts upon
power-up. The supply current during the under-voltage lockout period is
typically less than 150µA, and the outputs are actively forced to the low
state.
(continued)
Device
UVLO
Outputs
“Fixed”
1861
16.5/10.5
Alternating
Off Time
BLOCK DIAGRAM
1862
16.5/10.5
Parallel
Off Time
1863
36014
Alternating
Off Time
1864
36014
Parallel
Off Time
1865
16.5/10.5
Alternating
On Time
1866
16.5/10.5
Parallel
On Time
1867
36014
Alternating
On Time
1868
36014
Parallel
On Time
Pin numbers refer to the J and N packages.
10/98
UDG-92018




UC1861 pdf, 반도체, 판매, 대치품
UC1861-1868
UC2861-2868
UC3861-3868
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°CTA125°C for the
UC186x, –25°CTA85°C for the UC286x, and 0°CTA70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,
C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
UVLO
Vcc Turn-on Threshold
UCx861, UCx862, UCx865, UCx866
15 16.5 18
V
UCx863, UCx864, UCx867, UCx868
7 8.0 9
V
Vcc Turn-off Threshold
UCx861, UCx862, UCx865, UCx866
9.5 10.5 11.5 V
UCx863, UCx864, UCx867, UCx868
6 7.0 8
V
Icc Start
VCC = VCC(on) – 0.3V
150 300 µA
Icc Run
VID = 100mV
25 32 mA
Note 1: Currents are defined as positive into the pin.
Note 2: Pulse measurement techniques are used to insure that TJ = TA.
Note 3: VID = V(NI) – V(INV).
Note 4: This parameter is not 100% tested in production but guaranteed by design.
Note 5: Vi = 0 to 4V
tr(Vi) 10ns tpd = t(Vo = 6V) – t(Vi = 3V)
APPLICATION INFORMATION
UVLO & 5V GENERATOR (See Figure 1): When power
is applied to the chip and Vcc is less than the upper
UVLO threshold, Icc will be less than 300µA, the 5V gen-
erator will be off, and the outputs will be actively held low.
When Vcc exceeds the upper UVLO threshold, the 5V
generator turns on. Until the 5V pin exceeds 4.9V, the
outputs will still remain low.
The 5V pin should be bypassed to signal ground with a
0.1µF capacitor. The capacitor should have low equiva-
lent series resistance and inductance.
FAULT AND SOFT-REFERENCE (See Figure 1): The
Soft-Ref pin serves three functions: system reference, re-
start delay, and soft-start. Designed to source or sink
200µA, this pin should be used as the input reference for
the error amplifier circuit. This pin requires a bypass ca-
pacitor of at least 0.1µF. This yields a minimum soft-start
time of 1ms.
Under-Voltage Lockout sets both the fault and restart de-
lay latches. This holds the outputs low and discharges
the Soft-Ref pin. After UVLO, the fault latch is reset by
the low voltage on the Soft-Ref pin. The reset fault latch
resets the delay latch and Soft-Ref charges via the 0.5mA
current source.
The fault pin is input to a high speed comparator with a
threshold of 3V. In the event of a detected fault, the fault
latch is set and the outputs are driven low. If Soft-Ref is
above 4V, the delay latch is set. Restart delay is timed as
Soft-Ref is discharged by 20µA. When Soft-Ref is fully
discharged, the fault latch is reset if the fault input signal
is low. The Fault pin can be used as a system shutdown
pin.
If a fault is detected during soft-start, the fault latch is set
and the outputs are driven low. The delay latch will re-
main reset until Soft-Ref charges to 4V. This sets the de-
lay latch, and restart delay is timed. Note that restart
delay for a single fault event is longer than for recurring
faults since Soft-Ref must be discharged from 5V instead
of 4V.
The restart delay to soft-start time ratio is 24:1 for a fault
occurring during normal operation and 19:1 for faults oc-
curring during soft-start. Shorter ratios can be pro-
grammed down to a limit of approximately 3:1 by the
addition of a 20kor larger resistor from Soft-Ref to
ground.
A 100kresistor from Soft-Ref to 5V will have the effect
of permanent shut down after a fault since the internal
20µA current source can't pull Soft-Ref low. This feature
can be used to require recycling Vcc after a fault. Care
must be taken to insure Soft-Ref is indeed low at start up,
or the fault latch will never be reset.
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UC1861 전자부품, 판매, 대치품
APPLICATION INFORMATION
Minimum oscillator frequency is set by Rmin and Cvco.
The minimum frequency is approximately given by the
equation:
4.3
FMIN RMIN CVCO
Maximum oscillator frequency is set by Rmin, Range &
Cvco. The maximum frequency is approximately given by
the equation:
3.3
FMAX (RMIN / / Range ) CVCO
UC1861-1868
UC2861-2868
UC3861-3868
The Error Amplifier directly controls the oscillator fre-
quency. E/A output low corresponds to minimum fre-
quency and output high corresponds to maximum
frequency. At the end of each oscillator cycle, the RC pin
is discharged to one diode drop above ground. At the be-
ginning of the oscillator cycle, V(RC) is less than Vth1
and so the output of the zero detect comparator is ig-
nored. After V(RC) exceeds Vth1, the one shot pulse will
be terminated as soon as the zero pin falls below 0.5V or
V(RC) exceeds Vth2. The minimum one shot pulse width
is approximately given by the equation:
Tpw(min) 0.3 R C.
The maximum pulse width is approximately given by:
Tpw(max) 1.2 R C.
STEERING LOGIC
UDG-92013
The steering logic is configured on the UC1861,63 to result in
dual non-overlapping square waves at outputs A & B. This is
suited to drive dual switch ZVS systems.
UDG-92014
The steering logic is configured on the UC1862,64 to result in
inverted pulse trains occurring identically at both output pins.
This is suited to drive single switch ZVS systems. Both outputs
are available to drive the same MOSFET gate. It is advisable
to join the pins with 0.5 ohm resistors.
UDG-92015
The steering logic is configured on the UC1865,67 to result in
alternating pulse trains at outputs A & B. This is suited to drive
dual switch ZCS systems.
UDG-92016
The steering logic is configured on the UC1866,68 to result in
non-inverted pulse trains occurring identically at both output
pins. This is suited to drive single switch ZCS systems. Both
outputs are available to drive the same MOSFET gate. It is ad-
visable to join the pins with 0.5 ohm resistors.
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