PDF GF9101 Data sheet ( Hoja de datos )

Número de pieza	GF9101
Descripción	High Performance Multirate Digital Filter
Fabricantes	Gennum
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No Preview Available ! www.DataSheet4U.com MultiGEN ™ GF9101 High Performance Multirate Digital Filter FEATURES • highly optimized & flexible architecture for multirate FIR filtering applications • implements dual 12 tap filters operating at 40 MHz or single 23 or 24 tap filter operating at 20 MHz maximum data rate • stores up to 108 fully-programmable 12 tap filters with 12 bit coefficients at each tap, dynamically addressable in each clock cycle • 3 flexible memory loading modes • 20 bit pipeline for cascading up to 3 devices • 20 bit output accumulator • filter output negate and zero controls • supports both symmetrical and asymmetrical FIR filters • 40 MHz maximum computation and input/output data rates DESCRIPTION DATA SHEET The GF9101 is a high performance multirate digital filter which can be programmed to implement a wide range of signal processing functions using both symmetrical and asymmetrical filter structures. It is composed of a 12-tap FIR filter with internal RAM to hold up to 108 individual filters. An externally controlled address bus selects one of the 108 filters in each clock cycle. Pipelined architecture allows cascading of up to three devices with no additional hardware. Two 10-bit input shift registers are provided for multiplexed filtering applications. The 12-bit coefficients can be programmed in serial, high speed parallel or microprocessor modes. In the high speed parallel mode, any one of the 108 filters can be reprogrammed in 18 clock cycles. ORDERING INFORMATION APPLICATIONS Video rate conversion; High performance FIR filters; Adaptive digital filters; Video encoding; Digital modulation PART NUMBER GF9101 - CMQ PACKAGE 160 pin Metal Quad TEMPERATURE 0° to 70°C +10 DATA–A–IN ENA +10 DATA–B–OUT ENB R R SEL–A/B ENC R R COEF–ADDR R 1 0 TAP TAP CELL CELL 12 7 TAP CELL 11 7 +10 DATA–A–OUT +10 TAP DATA–B–IN CELL 12 ZERO NEGATE R R Σ ±14.11 4R ±13.6 TRUNCATED DELAY 1,3,4,5 2 R DELAY SEL ±13.6 CONFIGURATION REGISTER DATA B SEL PIPELINE–IN ±13.6 CARRY IN ±13.6 R ±13.6 0+ 1 ±13.6 R ±13.6 PIPELINE–OUT Revision Date: July 1999 FB–SEL R BLOCK DIAGRAM GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com Document No. 520 - 64 - 7 1 page The timing diagram shown in Figure 1 loads the memories shown in Table 4: TABLE 4: Memory Loaded into Internal RAM in Parallel Load Mode TAP (location) 12-bit WORD IN HEX. MEMORY BANK 1 (0) FB2 MB0 2 (0) EF4 MB0 11 (107) CCC MB5 12 (107) DDD MB5 CONFIGURE LOAD_EN COEF_WR COEF_DATA (7-0) COEF_ADDR (9-0) XX F4 2E FB DD CD XX 300 380 000 36B 3EB CLK_IN Fig. 1 Parallel Loading Timing Diagram The address generated is shown in Table 5. Timing for the parallel loading signals is the same as that for other synchronous inputs. TABLE 5: Address Generation for Parallel Loading Example DESTINATION COEF_ADDR (9-7) IN BINARY COEF_ADDR (6-0) IN HEX COEF_ADDR (9-0) IN HEX TEMP_REG_A 110 X 300 TEMP_REG_B 111 X 380 MB0 000 0 000 TEMP_REG_A 110 X 36B or 300 TEMP_REG_B 111 X 3EB or 380 MB5 101 6B 2EB CC 2EB XX XX MICROPROCESSOR LOADING If microprocessor loading is selected, the LOAD_EN pin alone determines the run mode or the load mode. When LOAD_EN is low, the load mode is selected, the run mode is disabled, but a write will not occur until COEF_WR is low. Microprocessor loading is random access and asynchronous. Like parallel loading, microprocessor loading uses COEF_DATA (7-0) and COEF_ADDR (9-0) to write three 8-bit words for each 24-bit memory written. Addressing is the same as for parallel loading. In microprocessor mode, at least one set of filter coefficients 5 520 - 64 - 7 5 Page TABLE 9: Configuration Word for a 24-tap Symmetric Filter BIT CONFIG. NO. WORD DESCRIPTION 0 1 3Data A and B are both signed data 11 2 0 One register delay 30 4 0 24-tap filter, connect the outputs of DATA_A_OUT to the inputs of DATA_B_IN. 5 X Depending on the loading mode 6 X See Table 1 NOTE 3. Bits 0 and 1 should have the same value for a 23 or 24 tap filter The filter coefficients are shown in Figure 10. The timing is verysimilar to that of the even-symmetric case. C11 C11 C10 C10 C0 C3 C4 C5 C9 C2 C1 C6 C8 C7 A17 A18 A16 A19 A15 C9 C5 C4 C3 C0 (a) Filter Coefficients Cn C8 C6 C7 A7 A8 A6 A9 A5 C2 C1 (b) Input Data An A24 A23 A20 A21 A22 A14 A13 A10 A11 A12 A4 A0 A3 A1 A2 Fig. 10 Input Data An and Coefficients Cn ASYMMETRIC FILTER The GF9101 can be used as a 24-tap asymmetric filter by configuring it the same way as the even-symmetric case. The difference is in the memory locations since the asymmetric case uses 24 different coefficients, i.e. two sets of filter coefficients. The filter coefficients and the memory locations are shown in Table 10. The timing diagram is shown in Figure 11. The data flow diagrams are shown in Figures 11a and 11b. TABLE 10:Internal RAM Address & Contents for a 24-tap Asymmetric Filter COEF_ADDR (6-0) MEMORY CONTENTS 00H First set of 12 coefficients, C0 —> C11 01H Second set of 12 coefficients, C23 —> C12 11 520 - 64 - 7 11 Page

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