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부품번호 NX25P20 기능
기능 (NX25P10 - NX25P40) 1M BIT 2M BIT AND 4M BIT SERIAL FLASH MEMORY
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NX25P20 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
APRIL 2005
1M-BIT, 2M-BIT AND 4M-BIT
Serial Flash Memory with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1




NX25P20 pdf, 반도체, 판매, 대치품
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
FEATURES
GENERAL DESCRIPTION
• 1M / 2M / 4M-bit Serial Flash Memories
• Family of Serial Flash Memories
– NX25P10: 1M-bit / 128K-byte (131,072 ) 512 pages
– NX25P20: 2M-bit / 256K-byte (262,144 ) 1024 pages
– NX25P40: 4M-bit / 512K-byte (524,288 ) 2048 pages
– 256-bytes per programmable page
– Compatible migration path to 8M/16M/32M-bit
• 4-pin SPI Serial Interface
– Clock, Chip Select, Data In, Data Out
– Easily interfaces to popular microcontrollers
– Compatible with SPI Modes 0 and 3
– Optional Hold function for SPI flexibility
• Low Power Consumption,WideTemperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, 1µA Power-down (typ)
– -40° to +85°C operating range
• Fast and Flexible Serial Data Access
– Clock operation to 40MHz Fast Read, 33MHz
Standard Read
– Byte-addressable Read and Program
– Auto-increment Read capability
– Manufacturer and Device ID
• Programming Features
– Page program up to 256 bytes <2ms
– Sector Erase (64K-byte) 2 seconds
– Chip erase: 3 seconds (25P10/20),
5 seconds (25P40)
– 100,000 erase/write cycles
– Twenty year data retention
The NX25P10 (1M-bit), NX25P20 (2M-bit) and NX25P40
(4M-bit) Serial Flash memories provide a storage solution
for systems with limited space, pins and power. They are
ideal for code download applications as well as storing
voice, text and data. The devices operate on a single 2.7V
to 3.6V power supply with current consumption as low as
4mA active and 1µA for power-down. All devices are offered
in space-saving 8-pin SOIC type packages as shown
below. Contact NexFlash for availability of alternate pack-
ages. As part of a family of Serial Flash products,
NexFlash also provides a compatible migration path to 8M/
16M/32M-bit densities.
The NX25P10/20/40 array is organized into 512/1024/2048
programmable pages of 256-bytes each. A single byte or,
up to 256 bytes, can be programmed at a time using the
Page Program instruction. Pages are grouped into 2/4/8
erasable sectors of 256 pages (64K-byte) each as shown in
figure 1. Both Sector Erase and Bulk (full chip) Erase
instructions are supported.
The Serial Peripheral Interface (SPI) consists of four pins
(Serial Clock, Chip Select, Serial Data In and Serial Data
Out) that support high speed serial data transfers up to
40MHz. A Hold pin, Write Protect pin and programmable
write protect features provide further control flexibility.
Additionally, the device can be queried for manufacturer
and device ID. Special customer ID (for copy authentica-
tion) and factory programming is available, contact Nex-
Flash for more information.
• Software and Hardware Write Protection
– Write-Protect all or portion of memory via software
– Enable/Disable protection with WP pin
8-Pin SOIC 150-mil
(Package Code N)
• Space Saving Package
– Tiny 8-pin SOIC
• Ideal for systems with limited pins, space, and power
– ASIC and Controller-based serial code-download
– Microcontroller systems storing data, text or voice
– Battery-operated and portable products
4 NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©

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NX25P20 전자부품, 판매, 대치품
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
SPI OPERATION
SPI Modes
The NX25P10/20/40 is accessed through an SPI compat-
ible bus consisting of four signals: Serial Clock (CLK), Chip
Select (CS), Serial Data Input (DI) and Serial Data Output
(DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are
supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when
the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0 the CLK signal
is normally low. For Mode 3 the CLK signal is normally high.
In either case data input on the DI pin is sampled on the
rising edge of the CLK. Data output on the DO pin is clocked
out on the falling edge of CLK.
Hold Function
The HOLD signal allows the NX25P10/20/40 operation to be
paused while it is actively selected (when CS is low). The
hold function may be useful in cases where the SPI data and
clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the
hold function can save the state of the instruction and the
data in the buffer so programming can resume where it left
off once the bus is available again.
To initiate a hold condition, the device must be selected with
CS low. A hold condition will activate on the falling edge of
the HOLD signal if the CLK signal is already low. If the CLK
is not already low the hold condition will activate after the
next falling edge of CLK. The hold condition will terminate
on the rising edge of the hold signal if the CLK signal is
already low. If the CLK is not already low the hold condition
will terminate after the next falling edge of CLK.
During a hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DI) and Serial Clock
(CLK) are ignored. The Chip Select (CS) signal should be
kept active (low) for the full duration of the hold operation to
avoid resetting the internal logic state of the device.
WRITE PROTECTION
Applications that use non-volatile memory must take into
consideration the possibility of noise and other adverse
system conditions that may compromise data integrity. To
address this concern the NX25P10/20/40 provides several
means to protect data from inadvertent writes.
Write Protect Features
• Device resets when Vcc is below threshold.
1
• Time delay write disable after Power-up.
• Write enable/disable instructions.
• Automatic write disable after program and erase.
2
• Software write protection using Status Register.
3• Hardware write protection using Status Register and
WP pin.
• Write Protection using Power-down instruction.
Upon power-up or at power-down the NX25P10/20/40 will
maintain a reset condition while Vcc is below the threshold
value of VWI, (See Power-up Timing and Voltage Levels:
Table 7 and Figure 17). While reset, all operations are
disabled and no instructions are recognized. During power-
up and after the Vcc voltage exceeds VWI, all program and
erase related instructions are further disabled for a time
delay of tPUW. This includes the Write Enable, Page Pro-
gram, Sector Erase, Bulk Erase and the Write Status
Register instructions. Note that the chip select pin (CS)
must track the Vcc supply level at power-up until the Vcc-
min level and tVSL time delay is reached. If needed a pull-up
resister on CS can be used to accomplish this.
4
5
6
7
After power-up the device in automatically placed in a write-
disabled state with the Status Register Write Enable Latch
8(WEL) set to a 0. A Write Enable instruction must be issued
before a Page Program, Sector Erase, Bulk Erase or Write
Status Register instruction will be accepted. After complet-
ing a program, erase or write instruction the Write Enable
9Latch(WEL)isautomaticallycleared toawrite-disabledstate
of 0.
Software controlled write protection is facilitated using the
1 0Write Status Register instruction and setting the Status
Register Protect (SRP) and Block Protect (BP0, BP2) bits.
These Status Register bits allow a portion or all of the
memory to be configured as read only. Used in conjunction
1 1with the Write Protect (WP) pin, changes to the Status
Register can be enabled or disabled under hardware control.
See Status Register for further information.
1 2Additionally, the Power-down instruction offers an extra
level of write protection as all instructions are ignored
except for the Release Power-down instruction.
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
7

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(NX25P10 - NX25P40) 1M BIT 2M BIT AND 4M BIT SERIAL FLASH MEMORY

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