AN1504D Datasheet PDF - ON Semiconductor
| Part Number | AN1504D | |
| Description | Metastability and the ECLinPS Family | |
| Manufacturers | ON Semiconductor | |
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AN1504/D
Metastability and the
ECLinPS Family
Prepared by: Applications Engineering
This application note examines the concept of
metastability and provides a theoretical discussion of how it
occurs, including examples of the metastable condition. An
equation characterizing metastability and a test circuit
derived from that equation are presented. Metastability
results are then applied to the ECLinPS family.
Introduction
Metastability is a central issue anytime a designer wishes
to synchronize two or more asynchronous signals. A popular
method for accomplishing this task is to employ a D
flip−flop as the synchronizing element (Figure 1).
As shown in Figure 1, synchronization can be
accomplished using a single D flip−flop; more typically,
several D flip−flops are cascaded to provide synchronization
while reducing the probability of a metastable or
“anomalous” state occurring at the input of System 2.
Unfortunately the information at the data and clock inputs of
flip−flops used as synchronizing elements is asynchronous by
nature, thus the manufacturer specifications for set−up and
hold times may not be observed. A series of timing diagrams
is shown in Figure 2 demonstrating three possible timing
relationships between the data and clock signals; to the right
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APPLICATION NOTE
of each data trace is the corresponding output waveform. In
the first case the data adheres to the specified set−up and hold
times, hence the output attains the proper state. In case 2 the
set−up time is violated such that the output of the D flip−flop
does not change state. Case 3 represents a violation of the
set−up and hold times whereby the D flip−flop enters a
metastable state. The resolving time for a flip−flop in this
metastable state is indeterminate. Further, the final settling
state of the flip−flop having been in this metastable condition
cannot be guaranteed.
Metastability Theory
A bistable device such as a flip−flop has two stable output
states: the “1” or high state and the “0” or low state. When
the manufacturers specified set−up and hold times are
observed the flip−flop will achieve the proper output state
(Figure 3). However if the set−up and hold times are
violated the device may enter a metastable state, thereby
increasing the propagation delay, as indicated by the output
response shown in Figure 4.
To better understand flip−flop metastability, the operation
of a typical ECLinPS D flip−flop is reviewed. The schematic
of a D flip−flop is shown in Figure 5.
SYSTEM 1
CLOCK
SYSTEM 2
CLOCK
SYSTEM 1
CLOCK
SYSTEM 2
CLOCK
SYSTEM 1
SYSTEM 1
OUTPUT
SYSTEM 1
SYSTEM 1
OUTPUT
DATA
Q
D FLIP−FLOP
CLOCK
DATA
Q
D FLIP−FLOP
CLOCK
DATA
Q
D FLIP−FLOP
CLOCK
SYSTEM 2 INPUT
SYSTEM 2
SYSTEM 2 INPUT
SYSTEM 2
TD DELAY
Figure 1. Clock Synchronization Schemes
Semiconductor Components Industries, LLC, 2004
November, 2004 − Rev. 2
1
Publication Order Number:
AN1504/D
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AN1504/D
This equation only applies for narrow window widths, i.e.,
those times well up on the response plot of Figure 6.
To summarize, when the set−up and hold times are obeyed
the flip−flop will have a nominal propagation delay, TP. If
the data and clock signals arrive such that the set−up and
hold times are violated there will be an excess delay as
indicated in the response plot of Figure 6. This excess delay
is caused by the flip−flop entering the metastable region. For
data signals arriving much later than the clock signal the
flip−flop will not change state, thus the propagation delay is
zero by definition. The window width is the range of input
arrival times relative to the clock for which the output
response does not attain a defined value within the time
period TD. Since TD represents the maximum allowable
delay, the window width represents the relative range of
input times for which a failure will occur.
Equation 1 can be combined with the industry accepted
definition for system level Mean Time Between Failures
(Equation 2)2 to derive an equation yielding Mean Time
Between Failures as a function of system design and
semiconductor device parameters.
MTBF + 1ń(2 * fC * fD * TW(TD))
(eq. 2)
Where:
fC Clock Frequency
fD Data Frequency
MTBF + 1ń(2 * fC * fD * TP * 10 * (Dt)ńt) (eq. 3)
The System Designer can use Equation 3 to address the
issue of metastability. Device t values are provided in
Table 2, “ t Values for Several Flip−Flops” and TP
(Nominal Propagation Delay) value is provided in the
device datasheet. MTBF, fc and fd are system design
parameters. Thus the designer can use this equation to
determine the value of TD.
Test Circuitry For Metastable Evaluation
Equation 3 provides the impetus for the design of a
metastability test circuit capable of providing a value of t,
the flip−flop resolution time constant. Transforming this
equation into a “linear” form by taking the logarithm of both
sides yields Equation 4:
log MTBF + * log @ (2 * fC * fD * TP) ) Dtńt (eq. 4)
Plotting log MTBF versus Dt yields a line with slope 1/t,
and log MTBF intercept of −log(2*fc*fd*TP). Thus, the test
circuit must accept the clock and data input frequencies as
a function of Dt and yield MTBF as an output. The circuit
configuration shown in Figure 9 fulfills these criteria.
The test circuitry can be categorized into five functional
blocks: DUT, adjustable delay portion, comparator section,
counter−set circuitry, and the counter. Starting with the
comparator portion of the circuit, the output of the DUT is
fed into the comparator; if the DUT output falls in the range
VBB − 0.15 V < VBB < VBB + 0.15 V, the DUT is defined as
being in a metastable condition (Figure 10).
For DUT output states in the metastable region the
comparator output attains a logic high level. When the DUT
output does not fall within this range it is in a “defined high
or low level,” and the output of the comparator will be at a
logic low level. If the comparator output is at a logic high
level, indicating metastability, the counter−set section sends
out a periodic waveform which increments the counter. If the
DUT is not metastable the output of the “counter−set”
circuitry is constant and the counter (HP−8335A) is not
incremented. The total number of counts over a specified
time period is a measure of MTBF.
Q
HP−
8082A
Q
HP−
8082A
Q
TRIG
HP−
Q
8082A
Q
DUT
D
Q
DUT
CLK 1
(VBB + 0.15 V)
10E451
D1
D1
D2
D2
CLK 2
CLK 2
Q1
Q2
(VBB − 0.15 V)
10E107
DQ
10E131
CLK 3
10E101
HP 5335A
COUNTER
COUNTER
ADJUSTABLE DELAY
COMPARATOR
Figure 9. Metastability Test Circuit
COUNTER−SET
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