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ADCMP603 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADCMP603은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ADCMP603 기능
기능 Single-Supply TTL/CMOS Comparator
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ADCMP603 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
ADCMP603
FEATURES
Fully specified rail to rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch CMOS-/TTL-compatible output stage
Complementary outputs
3.5 ns propagation delay
12 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP603 is a very fast comparator fabricated on
XFCB2, an Analog Devices, Inc. proprietary process. This
comparator is exceptionally versatile and easy to use. Features
include an input range from VEE − 0.5 V to VCC + 0.2 V, low noise
complementary TTL-/CMOS-compatible output drivers, latch
inputs with adjustable hysteresis and a shutdown input.
The device offers 3.5 ns propagation delay with 10 mV
overdrive on 4 mA typical supply current.
A flexible power supply scheme allows the device to operate
with a single +2.5 V positive supply and a −0.5 V to +2.8 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions support a wide input signal range while
still allowing independent output swing control and power
savings.
FUNCTIONAL BLOCK DIAGRAM
VCCI
VCCO
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP603
TTL
Q OUTPUT
Q OUTPUT
LE/HYS INPUT
SDN INPUT
Figure 1.
The device passes 4.5 kV HBM ESD testing and the absolute
maximum ratings include current limits for all pins.
The complementary TTL-/CMOS-compatible output stage is
designed to drive up to 5 pF with full timing specs and to
degrade in a graceful and linear fashion as additional
capacitance is added. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
Latch and programmable hysteresis features are also provided
with a unique single-pin control option.
The ADCMP603 is available in a 12-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




ADCMP603 pdf, 반도체, 판매, 대치품
ADCMP603
Parameter
AC PERFORMANCE1
Rise Time /Fall time
Propagation Delay
Propagation Delay Skew—Rising to
Falling Transition
Propagation Delay Skew—Q to QB
Overdrive Dispersion
Common-Mode Dispersion
Minimum Pulse Width
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential
Positive Supply Differential
Input Section Supply Current
Output Section Supply Current
Power Dissipation
Power Supply Rejection Ratio
Shutdown Mode Supply Current
Symbol Conditions
tR/tF
tPD
tPINSKEW
tDIFFSKEW
PWMIN
10% to 90%, VCCO = 2.5 V
10% to 90%, VCCO = 5.5 V
VOD = 50 mV, VCCO = 2.5 V
VOD = 50 mV, VCCO = 5.5 V
VOD = 10 mV, VCCO = 2.5 V
VCCO = 2.5 V to 5.5 V
VOD = 50 mV
VCCO =2.5 V to 5.5 V
VOD = 50 mV
10 mV < VOD < 125 mV
−2 V < VCM < VCCI + 2 V
VOD = 50 mV
VCCI = VCCO = 2.5 V
PWOUT = 90% of PWIN
VCCI = VCCO = 5.5 V
PWOUT = 90% of PWIN
VCCI
VCCO
VCCI − VCCO
VCCI − VCCO
IVCCI
IVCCO
PD
PD
PSRR
Operating
Nonoperating
VCCI = 2.5 V to 5.5 V
VCCI = 2.5 V to 5.5 V
VCC = 2.5 V
VCC = 5.5 V
VCCI = 2.5 V to 5.5 V
VCC =2.5 V
1 VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, VCCI = VCCO = 2.5 V, unless otherwise noted.
Min
2.5
2.5
−3.0
−5.5
−50
Typ
2.2
4.5
3.5
4.8
5
500
300
1.5
200
3.3
5.5
1.1
2.3
9
21
290
Max Unit
ns
ns
ns
ns
ns
ps
ps
ns
ps
ns
ns
5.5 V
5.5 V
+3.0 V
+5.5 V
1.8 mA
3.5 mA
11 mW
30 mW
dB
430 μA
Rev. 0 | Page 4 of 16

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ADCMP603 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCCO 1
VCCI 2
VEE 3
PIN 1
INDICATOR
ADCMP603
TOP VIEW
(Not to Scale)
9 VEE
8 LE/HYS
7 SDN
ADCMP603
Figure 3. ADCMP603 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCCO Output Section Supply.
2 VCCI Input Section Supply.
3 VEE Negative Supply Voltage.
4 VP Noninverting Analog Input.
5 VEE Negative Supply Voltage.
6 VN Inverting Analog Input.
7 SDN Shutdown. Drive this pin low to shut down the device.
8
LE/HYS
Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
9 VEE Negative Supply Voltage.
10 Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, if the comparator is in compare mode. See the LE/HYS pin description (Pin 8)
for more information.
11 VEE Negative Supply Voltage.
12 Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE pin description
(Pin 8) for more information.
Heat Sink VEE
Paddle
The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5,
Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if
improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the
heat sink paddle.
Rev. 0 | Page 7 of 16

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