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PDF ADCMP606 Data sheet ( Hoja de datos )
| Número de pieza | ADCMP606 | |
| Descripción | (ADCMP606 / ADCMP607) Single-Supply CML Comparators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
ADCMP606/ADCMP607
FEATURES
10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
CML-compatible output stage
1 ns propagation delay
50 mW at 2.5 V
Shutdown pin (ADCMP607 only)
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP606/ADCMP607 are very fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from VEE − 0.5 V to VCC + 0.5 V,
low noise CML-compatible output drivers, and TTL-/CMOS-
compatible latch inputs with adjustable hysteresis and/or
shutdown inputs.
The device offers 1 ns propagation delay with 2 ps RMS random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
FUNCTIONAL BLOCK DIAGRAM
VCCI
VCCO
(ADCMP607 Only)
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP606/
ADCMP607
CML
Q OUTPUT
Q OUTPUT
LE/HYS INPUT (ADCMP607 Only)
SDN INPUT (ADCMP607 Only)
Figure 1.
VCCO 1
VCCI 2
VEE 3
PIN 1
INDICATOR
ADCMP607
TOP VIEW
(Not to Scale)
9 VEE
8 LE/HYS
7 SDN
Figure 2.LFCSP Pin Configuration
to +6 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to support
a wide input signal range with independent output level control
and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, high speed latch and programmable hysteresis
features are also provided with a unique single-pin control option.
The ADCMP606 is available in a 6-lead SC70 package, and the
ADCMP607 is available in a 12-lead LSCFP package.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage
(VCCO to GND)
Positive Supply Differential
(VCCI − VCCO)
Input Voltages
Input Voltage
Differential Input Voltage
Maximum Input/Output Current
Shutdown Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Output Current
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
Rating
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−6.0 V to +6.0 V
−0.5 V to VCCI + 0.5 V
±(VCCI + 0.5 V)
±50 mA
−0.5 V to VCCO + 0.5 V
±50 mA
−0.5 V to VCCO + 0.5 V
±50 mA
±50 mA
−40°C to +125°C
150°C
−65°C to +150°C
ADCMP606/ADCMP607
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
ADCMP606 SC70 6-lead
ADCMP607 LSCFP 12-lead
θJA1 Unit
426 °C/W
62 °C/W
1 Measurement in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 16
5 Page 
Preliminary Technical Data
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 18 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure TBD illustrates hysteresis as a function of the current.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7k ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
Figure 18. Hysteresis vs. RHYS Control Resistor
ADCMP606/ADCMP607
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change.
The ADCMP606/ADCMP607 slightly elaborate on this scheme.
With VCC less than 4 V, this crossover is at the expected VCC/2,
but with VCC greater than 4 V, the crossover point instead follows
VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This
means that at any voltage, the comparator input characteristics
more closely resemble the inputs of nonrail-to-rail ground
sensing comparators, such as the AD8611.
MINIMUM INPUT SLEW RATE REQUIREMENT
(Remove if device is stable.)
As with most high speed comparators without hysteresis, a
minimum slew rate must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscillation
is due in part to the high input bandwidth of the comparator in
combination with feedback parasitics inherent in the package
and PC board. A minimum slew rate of TBD V/μs ensures clean
output transitions from the ADCMP606/ADCMP607 comparators
unless hysteresis is programmed. In many applications, chattering
due to the absence of hysteresis is not harmful.
Rev. PrA | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADCMP606.PDF ] | |
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