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ADM1067 데이터시트 PDF




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부품번호 ADM1067 기능
기능 Super Sequencer
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ADM1067 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Open-loop margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Super Sequencer with
Open-Loop Margining DACs
ADM1067
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1067
VREF
SMBus
INTERFACE
EEPROM
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCA P
MUP
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
VCCP
MDN
DAC1
DAC2
DAC3
DAC4
Figure 1.
DAC5
DAC6
GENERAL DESCRIPTION
The ADM1067 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1067 integrates six 8-bit voltage
output DACs. These circuits can be used to implement an open-
loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
For more information about the ADM1067 register map, refer
to the AN-698 Application Note.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADM1067 pdf, 반도체, 판매, 대치품
Data Sheet
REVISION HISTORY
1/15—Rev. D to Rev. E
Changes to Figure 3, Figure 4, and Table 4 ....................................9
Added Slew Rate Consideration Section......................................14
Added SCL Held Low Timeout Section and False Start
Detection Section ............................................................................26
Updated Outline Dimensions........................................................31
Changes to Ordering Guide...........................................................31
6/11—Rev. C to Rev. D
Changes to Serial Bus Timing Parameter in Table 1 ....................5
Change to Figure 3 ............................................................................9
Added Exposed Pad Notation to Outline Dimensions ..............31
Changes to Ordering Guide...........................................................31
5/08—Rev. B to Rev. C
Changes to Figure 1...........................................................................1
Changes to Table 1 ............................................................................4
Changes to Powering the ADM1067 Section ..............................13
Changes to Sequence Detector Section ........................................18
Changes to Figure 27 ......................................................................20
Changes to Configuration Download at Power-Up Section .....23
Changes to Table 10 ........................................................................24
Changes to Figure 40 and Error Correction Section..................29
Changes to Ordering Guide...........................................................30
ADM1067
11/06—Rev. A to Rev. B
Updated Format ................................................................. Universal
Changes to Features ..........................................................................1
Changes to Figure 2 ..........................................................................3
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................7
Changes to Absolute Maximum Ratings Section .........................9
Changes to Programming the Supply Fault Detectors Section ...14
Changes to Table 6 ..........................................................................14
Added the Default Output Configuration Section .....................18
Changes to Fault Reporting Section .............................................21
Changes to Figure 28 ......................................................................24
Changes to the Identifying the ADM1067
on the SMBus Section.....................................................................26
Changes to Figure 30 and Figure 31 .............................................28
Changes to Ordering Guide...........................................................32
1/05—Rev. 0 to Rev. A
Changes to Figure 1 ..........................................................................1
Changes to Absolute Maximum Ratings Section .........................8
Change to Supply Sequencing through Configurable
Output Drivers Section ..................................................................16
Changes to Figure 28 ......................................................................22
Change to Table 9............................................................................25
10/04—Revision 0: Initial Version
Rev. E | Page 3 of 31

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ADM1067 전자부품, 판매, 대치품
ADM1067
Data Sheet
Parameter
INL
DNL
Gain Error
Maximum Load Current (Source)
Maximum Load Current (Sink)
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
PSRR
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage Charge Pump Mode
(PDO1 to PDO6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Min Typ
100
100
2.043
1
2.5
60
40
2.048
−0.25
0.25
60
500
11 12.5
10.5 12
20
2.4
VPU − 0.3
0
16 20
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXx, A0, A1, MUP, MDN)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
90
2.0
−1
2.0
100
5
20
Max Unit Test Conditions/Comments
±0.75 LSB Endpoint corrected
±0.4 LSB
1%
μA
μA
50 pF
2 μs
mV Per mA
dB DC
dB 100 mV step in 20 ns with 50 pF load
2.053
V
mV
mV
μF
dB
No load
Sourcing current, IDACxMAX = −100 μA
Sinking current, IDACxMAX = 100 μA
Capacitor required for decoupling, stability
DC
14 V IOH = 0 μA
13.5 V
IOH = 1 μA
μA 2 V < VOH < 7 V
V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V
VPU to VPx = 6.0 V, IOH = 0 mA
V VPU ≤ 2.7 V, IOH = 0.5 mA
0.50 V
IOL = 20 mA
20 mA Maximum sink current per PDOx pin
60 mA Maximum total sink for all PDOx pins
29 kΩ Internal pull-up
2 mA Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
10 μA VPDO = 14.4 V
110 kHz All on-chip time delays derived from this clock
V Maximum VIN = 5.5 V
0.8 V
Maximum VIN = 5.5 V
μA VIN = 5.5 V
1 μA VIN = 0 V
pF
μA VDDCAP = 4.75 V, TA = 25°C, if known logic state is required
V
0.8 V
0.4 V
IOUT = −3.0 mA
Rev. E | Page 6 of 31

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