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PDF ADN2815 Data sheet ( Hoja de datos )
| Número de pieza | ADN2815 | |
| Descripción | Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Serial data input: 10 Mb/s to 1.25 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
APPLICATIONS
SONET OC-1/-3/-12 and all associated FEC rates
Fibre Channel, GbE, HDTVs
WDM transponders
Regenerators/repeaters
Test equipment
Broadband crossconnects and routers
Continuous Rate 10 Mb/s to 1.25 Gb/s
Clock and Data Recovery IC
ADN2815
GENERAL DESCRIPTION
The ADN2815 provides the receiver functions of quantization
and clock and data recovery for continuous data rates from
10 Mb/s to 1.25 Gb/s. The ADN2815 automatically locks to all
data rates without the need for an external reference clock or
programming. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The ADN2815 is available in a compact 5 mm × 5 mm 32-lead
LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2 VCC VEE
PIN
NIN
VREF
FREQUENCY
DETECT
LOOP
FILTER
BUFFER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
VCO
DATA
RE-TIMING
2
2
ADN2815
DATAOUTP/ CLKOUTP/
DATAOUTN CLKOUTN
Figure 1.
DRVCC DRVEE DVCC DVEE
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
ADN2815
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High
Output Voltage Low
Differential Output Swing
Differential Output Swing
Output Offset Voltage
Output Impedance
LVDS Outputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
I2C INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Conditions
VOH (see Figure 3), 655 Mb/s
VOL (see Figure 3), 655 Mb/s
VOD (see Figure 3), 655 Mb/s
VOD (see Figure 3), 1.25 Gb/s
VOS (see Figure 3)
Differential
20% to 80%
80% to 20%
TS (see Figure 2), GbE
TH (see Figure 2), GbE
LVCMOS
VIH
VIL
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 10
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
TR/TF
tSU;STO
tBUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
VIL
VIH
VIH
VIL
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
VOH, IOH = −2.0 mA
VOL, IOL = 2.0 mA
1 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
Min
Typ Max
Unit
925
250
240
1125
1475
320
300
1200
100
400
400
1275
mV
mV
mV
mV
mV
Ω
115 220
ps
115 220
ps
360
400 440
ps
360
400 440
ps
0.7 VCC
−10.0
0.3 VCC
+10.0
0.4
V
V
μA
V
600
1300
600
600
100
300
20 + 0.1 Cb1
600
1300
400 kHz
ns
ns
ns
ns
ns
ns
300 ns
ns
ns
0V
VCC V
100 mV p-p
10 160 MHz
100 ppm
2.0 V
0.8 V
5 μA
−5 μA
2.4 V
0.4 V
Rev. 0 | Page 5 of 24
5 Page 
JITTER SPECIFICATIONS
The ADN2815 CDR is designed to achieve the best bit-error-
rate (BER) performance and exceeds the jitter transfer, genera-
tion, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2815 performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms, and must be less than 0.1 UI p-p.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on an
input signal that can be transferred to the output signal (see
Figure 11).
ADN2815
0.1
ACCEPTABLE
RANGE
SLOPE = –20dB/DECADE
fC
JITTER FREQUENCY (kHz)
Figure 11. Jitter Transfer Curve
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 12).
15.00
SLOPE = –20dB/DECADE
1.50
0.15
f0 f1 f2 f3
JITTER FREQUENCY (kHz)
Figure 12. SONET Jitter Tolerance Mask
f4
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADN2815.PDF ] | |
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