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PDF CS5303 Data sheet ( Hoja de datos )
| Número de pieza | CS5303 | |
| Descripción | Three-Phase Buck Controller | |
| Fabricantes | ON Semiconductor | |
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CS5303
Three−Phase Buck
Controller with Integrated
Gate Drivers
The CS5303 is a three−phase step down controller which
incorporates all control functions required to power high performance
processors and high current power supplies. Proprietary multi−phase
architecture guarantees balanced load current distribution and reduces
overall solution cost in high current applications. Enhanced V2™
control architecture provides the fastest possible transient response,
excellent overall regulation, and ease of use.
The CS5303 multi−phase architecture reduces output voltage and
input current ripple, allowing for a significant reduction in inductor
values and a corresponding increase in inductor current slew rate. This
approach allows a considerable reduction in input and output capacitor
requirements, as well as reducing overall solution size and cost.
Features
• Enhanced V2 Control Method
• 5−Bit DAC with 1.0% Accuracy
• Adjustable Output Voltage Positioning
• 6 On−Board Gate Drivers
• 200 kHz to 800 kHz Operation Set by Resistor
• Current Sensed through Buck Inductors, Sense Resistors,
or V−S Control
• Hiccup Mode Current Limit
• Individual Current Limits for Each Phase
• On−Board Current Sense Amplifiers
• 3.3 V, 1.0 mA Reference Output
• 5.0 V and/or 12 V Operation
• On/Off Control (through COMP Pin)
http://onsemi.com
28
1
SO−28L
DW SUFFIX
CASE 751F
MARKING DIAGRAM
28
CS5303
AWLYYWW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
COMP
VFB
VDRP
CS1
CS2
CS3
CSREF
VID0
VID1
VID2
VID3
VID4
ILIM
REF
28ROSC
VCCLL1
Gate(L)1
Gnd1
Gate(H)1
VCCH12
Gate(H)2
GndL2
Gate(L)2
VCCL23
Gate(L)3
Gnd3
Gate(H)3
VCCH3
ORDERING INFORMATION
Device
Package
Shipping
CS5303GDW28
SO−28L 27 Units/Rail
CS5303GDWR28 SO−28L 1000 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 14
1
Publication Order Number:
CS5303/D
1 page  
CS5303
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 1.0 μF, ILIM ≥ 1 V;unless other-
wise specified)
Characteristic
Test Conditions
Min Typ
Max Unit
PWM Comparators
Minimum Pulse Width
Channel Start Up Offset
Measured from CSx to GATE(H)
V(VFB) = V(CSREF) = 1.0 V, V(COMP) = 1.5 V
60 mV step applied between VCSX and VCREF
−
350 515 ns
V(CS1) = V(CS2) = V(CS3) = V(VFB) = 0.3
0.4 0.5
−
V
V(CSREF) = 0 V; Measure V(COMP) when
GATE1(H), 2(H), 3(H) switch high
Gate(H) and Gate(L)
High Voltage (AC)
Low Voltage (AC)
Note 4 Measure VCCLX − Gate(L) or
VCCHX − Gate(H)
Note 4, Measure Gate(L) or Gate(H)
− 0 1.0 V
− 0 0.5 V
Rise Time Gate(H)x
Rise Time Gate(L)x
Fall Time Gate(H)x
Fall Time Gate(L)
Gate(H) to Gate(L) Delay
1.0 V < GATE < 8.0 V; VCCHX = 10 V
1.0 V < GATE < 8.0 V; VCCLX = 10 V
8.0 V > GATE > 1.0 V; VCCHX = 10 V
8.0 V > GATE > 1.0 V; VCCLX = 10 V
Gate(H) < 2.0 V, Gate(L) > 2 V
− 35 80 ns
− 35 80 ns
− 35 80 ns
− 35 80 ns
30 65 110 ns
Gate(L) to Gate(H) Delay
Gate(L) < 2.0 V, Gate(H) > 2 V
30 65 110 ns
GATE Pull−down
Oscillator
Force 100 μA into Gate Driver with no power
−
1.2
1.6
V
applied to VCCHX and VCCLX = 2 V.
Switching Frequency
Switching Frequency
Switching Frequency
ROSC Voltage
Phase Delay
Measure any phase (ROSC = 53.6 k)
Note 4 Measure any phase (ROSC = 32.4 k)
Note 4 Measure any phase (ROSC = 16.2 k)
−
−
220 250
280 kHz
300 400
500 kHz
600
800
1000
kHz
− 1.00
−
V
105 120
135 deg
Adaptive Voltage Positioning
VDRP Output Voltage to DACOUT
Offset
Maximum VDRP Voltage
Current Sense Amp to VDRP Gain
Current Sensing and Sharing
CS1 = CS2 = CS3 = CSREF, VFB = COMP
Measure VDRP − COMP
|(CS1 = CS2 = CS3) − CREF| = 50 mV,
VFB = COMP, Measure VDRP − COMP
−
−20 −
360 465
2.4 3.0
20 mV
570 mV
3.8 V/V
CS1−CS3 Input Bias Current
CSREF Input Bias Current
Current Sense Amplifiers Gain
V(CSx) = V(CSREF) = 0 V
−
−
− 0.2
− 0.6
3.8 4.3
2.0 μA
6.0 μA
4.8 V/V
Current Sense Amp Mismatch
(The sum of offset and gain errors)
Note 4 0 ≤ (CSx − CSREF) ≤ 50 mV
−5.0
−
5.0 mV
Current Sense Amplifiers Input
Common Mode Range Limit
Note 4 7 V < VCCLL1 < 12 V
0
−
VCCLL1 − 2
V
Current Sense Input to ILIM Gain
Current Limit Filter Slew Rate
0.25 V < ILIM < 1.20 V
Note 4
5.0 6.5
8.0 V/V
7.5 15.0 40.0 mV/μs
4. Guaranteed by design. Not tested in production.
http://onsemi.com
5
5 Page 
CS5303
SWNODE
VFB (VOUT)
CSA Out
COMP − Offset
CSA Out + VFB
T1 T2
Figure 10. Open Loop Operation
Inductive Current Sensing
For lossless sensing current can be sensed across the
inductor as shown below in Figure 11. In the diagram L is the
output inductance and RL is the inherent inductor resistance.
To compensate the current sense signal the values of R1 and
C1 are chosen so that L/RL = R1 × C1. If this criteria is met
the current sense signal will be the same shape as the
inductor current, the voltage signal at Cx will represent the
instantaneous value of inductor current and the circuit can be
analyzed as if a sense resistor of value RL was used as a sense
resistor (RS).
SWNODE
VOUT
R1
L
C1
RL
CS +
CSA
OFFSET
CSREF
+
+
+
VFB
DACOUT
COMP
E+ .A.
PWM-
COMP
+
considered when setting the ILIM threshold. If a more
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 9.
Current Sharing Accuracy
PCB traces that carry inductor current can be used as part
of the current sense resistance depending on where the
current sense signal is picked off. For accurate current
sharing, the current sense inputs should sense the current at
the same point for each phase and the connection to the
CSREF should be made so that no phase is favored. (In some
cases, especially with inductive sensing, resistance of the
pcb can be useful for increasing the current sense
resistance.) The total current sense resistance used for
calculations must include any pcb trace between the CS
inputs and the CSREF input that carries inductor current.
Current Sense Amplifier Input Mismatch and the value of
the current sense element will determine the accuracy of
current sharing between phases. The worst case Current
Sense Amplifier Input Mismatch is 5 mV and will typically
be within 3 mV. The difference in peak currents between
phases will be the CSA Input Mismatch divided by the current
sense resistance. If all current sense elements are of equal
resistance a 3 mV mismatch with a 2 mΩ sense resistance
will produce a 1.5 A difference in current between phases.
Operation at > 50% Duty Cycle
For operation at duty cycles above 50% Enhanced V2
will exhibit subharmonic oscillation unless a compensation
ramp is added to each phase. A circuit like the one on the left
side of Figure 12 can be added to each current sense network
to implement slope compensation. The value of R1 can be
varied to adjust the ramp size.
Gate(L)X
Switch Node
3 k R1
25 k
Figure 11. Lossless Inductive Current Sensing with
Enhanced V2
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
MMBT2222LT1
1 nF
0.1 μF
CSX
.01 μF
CSREF
Slope Comp
Circuit
Existing Current
Sense Circuit
Figure 12. External Slope Compensation Circuit
http://onsemi.com
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CS5303.PDF ] | |
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