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PDF CS5421 Data sheet ( Hoja de datos )
| Número de pieza | CS5421 | |
| Descripción | Dual Out of Phase Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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CS5421
Dual Out−of−Phase
Synchronous Buck
Controller with Remote
Sense
The CS5421 is a dual N−channel synchronous buck regulator
controller. It contains all the circuitry required for two independent
buck regulators and utilizes the V2™ control method to achieve the
fastest possible transient response and best overall regulation, while
using the least number of external components. The CS5421 features
out−of−phase synchronization between the channels, reducing the
input filter requirement. The CS5421 also provides undervoltage
lockout, Soft Start, built in adaptive FET non−overlap and remote
sense capability. The part is available in a 16 Lead SO Narrow package
allowing the designer to minimize solution size.
Features
• V2 Control Topology
• 150 ns Transient Response
• Programmable Soft Start
• 25 ns Gate Rise and Fall Times (with 1.0 nF load)
• 40 ns Adaptive FET Nonoverlap Time
• 100% Duty Cycle for Enhanced Transient Response
• Internal Slope Compensation
• 1.0 V 0.8% and 2.0% Error Amplifier References
• 150 kHz to 750 kHz Programmable Frequency Operation
• Switching Frequency Set by Single Resistor
• Out−Of−Phase Synchronization Between the Channels Reduces the
Input Filter Requirement
• Undervoltage Lockout
• On/Off Control Through Use of the COMP Pins
http://onsemi.com
SO−16
D SUFFIX
CASE 751B
PIN CONNECTIONS AND
MARKING DIAGRAM
1
GATE(H)1
GATE(L)1
PGND
LGND
SGND
VFFB1
VFB1
COMP1
16
GATE(H)2
GATE(L)2
PGND2
VCC
ROSC
VFFB2
VFB2
COMP2
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
CS5421GD16
CS5421GDR16
Package
Shipping
SO−16
SO−16
48 Units/Rail
2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 10
1
Publication Order Number:
CS5421/D
1 page  
CS5421
PACKAGE PIN DESCRIPTION (continued)
PACKAGE PIN #
16 Lead SO Narrow
10
11
12
13
14
PIN SYMBOL
VFB2
VFFB2
ROSC
VCC
PGND2
15 GATE(L)2
16 GATE(H)2
VCC
ROSC
FUNCTION
Error amplifier inverting input for channel 2.
Input for the channel 2 PWM comparator.
A resistor from this pin to ground sets switching frequency.
Input Power supply pin.
High Current ground for the GATE(H)2 and GATE(L)2 pins.
Low Side Synchronous FET driver pin for the channel 2 FET.
High Side Switch FET driver pin for the channel 2 FET.
BIAS
CURRENT
SOGUERNCE
RAMP1
RAMP2
VFFB1
VFFB2
8.6 V
7.8 V − VCC
−
+
S Q FAULT
Set
Dominant
R
− 0.25 V
E/A OFF
OSC
CLK1
CLK2
PWM
Comparator 1
−
+
FAULT
RAMP1
0.45 V
−
+ FAULT
PCWomMparator 2
RAMP2
S
Reset
Dominant
R
S
Reset
Dominant
R
VCC
VCC
VCC
VCC
5.0 μA
1.0 V
SGND
E/A1
0.45 V
−
1.0 V
E/A OFF 1.0 mA
−
+ E/A2
VFB COMP1 VFB2
COMP2
Figure 2. Block Diagram
FAULT
LGND
GATE(H)1
GATE(L)1
PGND1
GATE(H)2
GATE(L)2
PGND2
http://onsemi.com
5
5 Page 
CS5421
PSWH(OFF) = upper MOSFET switch−off losses;
VIN = input voltage;
IOUT = load current;
tRISE = MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
tFALL = MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/fSW = period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)
where:
PHFET(TOTAL) = total switching (upper) MOSFET losses;
PRMS(H) = upper MOSFET switch conduction Losses;
PSWH(ON) = upper MOSFET switch−on losses;
PSWH(OFF) = upper MOSFET switch−off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
TJ + TA ) [PHFET(TOTAL) RQJA]
where:
TJ = FET junction temperature;
TA = ambient temperature;
PHFET(TOTAL) = total switching (upper) FET losses;
RΘJA = upper FET junction−to−ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
PRMS(L) + IRMS2 RDS(ON)
+ [IOUT Ǹ(1.0 * D)]2 RDS(ON)
where:
PRMS(L) = lower MOSFET conduction losses;
IOUT = load current;
D = Duty Cycle;
RDS(ON) = lower FET drain−to−source on−resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PSWL + VSD ILOAD non−overlap time fSW
where:
PSWL = lower FET switching losses;
VSD = lower FET source−to−drain voltage;
ILOAD = load current;
Non−overlap time = GATE(L)−to−GATE(H)
or
GATE(H)−to−GATE(L) delay (from CS5421 data sheet
Electrical Characteristics section);
fSW = switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL) + PRMS(L) ) PSWL
where:
PLFET(TOTAL) = Synchronous (lower) FET total losses;
PRMS(L) = Switch Conduction Losses;
PSWL = Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
TJ + TA ) [PLFET(TOTAL) RQJA]
where:
TJ = MOSFET junction temperature;
TA = ambient temperature;
PLFET(TOTAL) = total synchronous (lower) FET losses;
RΘJA = lower FET junction−to−ambient thermal resistance.
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, VCC, and the CS5421 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
PCONTROL(IC) + ICC1VCC1 ) PGATE(H)1
) PGATE(L)1 ) PGATE(H)2 ) PGATE(L)2
where:
PCONTROL(IC) = control IC power dissipation;
ICC1 = IC quiescent supply current;
VCC1 = IC supply voltage;
PGATE(H) = upper MOSFET gate driver (IC) losses;
PGATE(L) = lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
PGATE(H) + QGATE(H) fSW VCC
where:
PGATE(H) = upper MOSFET gate driver (IC) losses;
QGATE(H) = total upper MOSFET gate charge at VCC;
fSW = switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
PGATE(L) + QGATE(L) fSW VGATE(L)
http://onsemi.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CS5421.PDF ] | |
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