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PDF EMG5DXV5T1 Data sheet ( Hoja de datos )
| Número de pieza | EMG5DXV5T1 | |
| Descripción | (EMG2DXV5T1 / EMG5DXV5T1) Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors | |
| Fabricantes | ON Semiconductor | |
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EMG2DXV5T1,
EMG5DXV5T1
Preferred Devices
Dual Bias Resistor
Transistors
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SOT−553 package which is designed for low power surface mount
applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Moisture Sensitivity Level: 1
• Available in 8 mm, 7 inch Tape and Reel
• Lead−Free Solder Plating
• Pb−Free Packages are Available
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Value
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
VCBO
VCEO
IC
50
50
100
THERMAL CHARACTERISTICS
Unit
Vdc
Vdc
mAdc
Characteristic
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C
Derate above 25°C
PD 230 (Note 1) mW
338 (Note 2)
1.8 (Note 1)
°C/W
2.7 (Note 2)
Thermal Resistance −
Junction-to-Ambient
RqJA
540 (Note 1)
370 (Note 2)
°C/W
Thermal Resistance −
Junction-to-Lead
RqJL
264 (Note 1)
287 (Note 2)
°C/W
Junction and Storage
Temperature Range
TJ, Tstg −55 to +150
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
© Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 0
1
http://onsemi.com
NPN SILICON
BIAS RESISTOR
TRANSISTORS
(3)
R1
R2
DTr2
(2)
R2
(1)
R1
DTr1
(4) (5)
5
1
SOT−553
CASE 463B
MARKING
DIAGRAM
5
XX M G
G
1
xx =
M=
G=
Device Code
xx= UF (EMG5)
UP (EMG2)
Date Code
Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
EMG5DXV5/D
1 page  
EMG2DXV5T1, EMG5DXV5T1
TYPICAL APPLICATIONS FOR NPN BRTs
+12 V
FROM mP OR
OTHER LOGIC
ISOLATED
LOAD
Figure 12. Level Shifter: Connects 12 or 24 Volt Circuits to Logic
+12 V
VCC
OUT
IN
LOAD
Figure 13. Open Collector Inverter:
Inverts the Input Signal
Figure 14. Inexpensive, Unregulated Current Source
http://onsemi.com
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