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부품번호 | NB2304A 기능 |
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기능 | Zero Delay Clock Buffer | ||
제조업체 | ON Semiconductor | ||
로고 | |||
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NB2304A
3.3 V Zero Delay
Clock Buffer
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks in PC, workstation, datacom, telecom
and other high−performance applications. It is available in an 8 pin
package. The part has an on−chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
input−to−output propagation delay is guaranteed to be less than
250 ps, and the output−to−output skew is guaranteed to be less than
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304Ax1H is the high−drive version of
the −1 and the rise and fall times on this device are much faster.
The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X
frequencies on each output Bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
Features
• Zero Input − Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
• Multiple Configurations − Refer to NB2304A Configurations Table
• Input Frequency Range: 15 MHz to 133 MHz
• Multiple Low−Skew Outputs
• Output−Output Skew < 200 ps
• Device−Device Skew < 500 ps
• Two Banks of Four Outputs
• Less than 200 ps Cycle−to−Cycle Jitter (−1, −1H, −5H)
• Available in Space Saving, 8 pin 150 mil SOIC Package
• 3.3 V Operation
• Advanced 0.35 m CMOS Technology
• Industrial Temperature Available
• These are Pb−Free Devices
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8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAM*
8
XXXX
ALYW
G
1
XXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1
Publication Order Number:
NB2304A/D
NB2304A
Table 6. SWITCHING CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min Typ Max
t1 Output Frequency
30 pF load (all devices)
15 pF load (−1, −2)
15 133
15 133.3
Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at
30 pF load
1.4
V,
FOUT
=
66.66
MHz
Measured at 1.4 V, FOUT v 50 MHz
15 pF load
40.0 50.0 60.0
45.0 50.0 55.0
t3 Output Rise Time
(−1, −2)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
2.20
1.50
Output Rise Time
(−1H)
Measured between 0.8 V and 2.0 V
30 pF load
1.50
t4 Output Fall Time
(−1, −2)
Measured between 2.0 V and 0.8 V
30 pF load
Measured between 2.0 V and 0.8 V
15 pF load
2.20
1.50
Output Fall Time
(−1H)
Measured between 2.0 V and 0.8 V
30 pF load
1.25
t5 Output−to−Output Skew on same Bank All outputs equally loaded
(−1, −2)
200
Output−to−Output Skew
(−1H)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew All outputs equally loaded
(−1)
200
Output Bank A−to−Output Bank B Skew All outputs equally loaded
(−2)
400
t6
Delay, REF Rising Edge to FBK Rising
Edge
Measured at VDD/2
0 ±250
t7 Device−to−Device Skew
Measured at VDD/2 on the FBK pins of the
device
0 500
t8 Output Slew Rate
Measured between 0.8 V and 2.0 V using
Test Circuit #2
1
tJ Cycle−to−Cycle Jitter
(−1, −1H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
175
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Cycle−to−Cycle Jitter
(−2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
400
375
tLOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF and FBK pins
1.0
Unit
MHz
%
ns
ns
ps
ps
ps
V/ns
ps
ps
ms
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4페이지 NB2304A
Zero Delay and Skew Control
For applications requiring zero input−output delay, all
outputs must be equally loaded.
1500
1000
500
0
−500
To close the feedback loop of the NB2304A, the FBK pin
can be driven from any of the four available output pins. The
output driving the FBK pin will be driving a total load of
7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input output delay. This is shown in Figure 3.
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use Figure 3 to calculate loading differences
between the feedback output and remaining outputs. For
zero output−output skew, be sure to load outputs equally.
−1000
−150−030 −25 −20 −15 −10 −5 0 5 10 15 20 25 30
OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF)
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
SWITCHING WAVEFORMS
1.4 V
t1
t2
1.4 V
1.4 V
Figure 4. Duty Cycle Timing
OUTPUT
2.0 V
0.8 V
t3
2.0 V
0.8 V
t4
3.3 V
0V
Figure 5. All Outputs Rise/Fall Time
OUTPUT
OUTPUT
1.4 V
t5
1.4 V
Figure 6. Output − Output Skew
INPUT
OUTPUT
VDD
2
t6
VDD
2
Figure 7. Input − Output Propagation Delay
FBK_Device 1
FBK_Device 2
VDD
2
VDD
2
t7
Figure 8. Device − Device Skew
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