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NB3N3001 데이터시트 PDF




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부품번호 NB3N3001 기능
기능 PureEdge Clock Generator
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NB3N3001 데이터시트, 핀배열, 회로
www.DataSheet4U.com
NB3N3001
3.3 V 106.25 MHz/ 212.5 MHz
PureEdge Clock Generator with
LVPECL Differential Output
Description
The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock
generator. It accepts a standard 26.5625 MHz fundamental mode AT cut
parallel resonant crystal as the reference source for its integrated crystal
oscillator and low noise phase−locked loop (PLL) and produces user
selectable clock frequencies of either 106.25 MHz or 212.5 MHz.
In addition, the PLL circuitry will generate a 50% duty cycle
square−wave through a pair of differential LVPECL clock outputs.
Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to
10 MHz.
The LVPECL output drivers can be disabled to high impedance with
the OE pin set LOW. The NB3N3001 operates from a single +3.3 V
supply, and is available in both plastic package and die form. The
operating temperature range is from −40°C to +85°C.
The NB3N3001 device provides the optimum combination of low
cost, flexibility, and high performance which makes it ideal for
Fibre−Channel applications.
Features
PureEdge Clock Family Provides Accuracy and Precision
Selectable Output Frequency of 106.25 MHz or 212.5 MHz
Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal
Fully Integrated Phase−Lock−Loop with Internal Loop Filter
Differential 3.3 V LVPECL Outputs
Exceeds Bellcore and ITU Jitter Generation Specification
RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal
(637 kHz − 10 MHz): 0.3 ps (Typical)
RMS Phase Noise at 106.25 MHz
Phase Noise:
Offset Noise Power
100 Hz −108 dBc/Hz
1 kHz −122 dBc/Hz
10 kHz −135 dBc/Hz
100 kHz −135 dBc/Hz
Operating Range: VCC = 3.135 V to 3.465 V
−40°C to +85°C Ambient Operating Temperature
Small Footprint 8−pin TSSOP Package
This is a Pb−Free Device
http://onsemi.com
TSSOP−8
DT SUFFIX
CASE 948S
MARKING
DIAGRAM
301
YWW
AG
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
FSEL
XIN
26.5625 MHz
XOUT
Crystal
Oscillator
Phase
Detector
Charge
Pump
VCO
850 MHz
M = B32
Figure 1. Logic Diagram
N =B8
orB4
LVPECL
Output
Q 212.5 MHz
or
Q 106.25 MHz
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 1
1
Publication Order Number:
NB3N3001/D




NB3N3001 pdf, 반도체, 판매, 대치품
NB3N3001
Table 10. AC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C (Note 4))
Symbol
Parameter
Conditions
Min Typ Max Unit
fOUT
Output Frequency
24 MHz − 30 MHz Crystal
(Typ. 25 MHz − 26.5625 MHz)
106.25/
212.5
MHz
tjit()
RMS Phase Jitter (Random)
(Note 3)
106.25 MHz; Integration Range:
637 kHz −10 MHz
0.3
ps
212.5 MHz; Integration Range:
637 kHz −10 MHz
0.3
tR/tF
Output Rise/Fall Time
20% to 80% (See Figure 7)
275
600 ps
odc Output Duty Cycle
(See Figure 6)
48 52 %
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Please refer to the Phase Noise Plot.
4. Output terminated with 50 W to VCC− 2.0 V. See Figures 4 and 12.
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise at 106.25 MHz
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NB3N3001 전자부품, 판매, 대치품
NB3N3001
PC Board Layout Example
Figure 11 shows a representative board layout for the
NB3N3001. There exists many different potential board
layouts and the one pictured is but one. The crystal X1
footprint shown in this example allows installation of either
surface mount HC49S or through−hole HC49 package. The
footprints of other components in this example are listed in
Table 11. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located
as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane. The
important aspect of the layout in Figure 11 is the low
impedance connections between VCC and GND for the
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the NB3N3001 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
The voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals
cross under the crystal as crosstalk energy coupled to these
lines could significantly impact the jitter of the device.
Table 11. Footprint Table
Reference
C1, C2
C3
C4, C5
R2
Size
0402
0805
0603
0603
C2
C1
Figure 11. PC Board Layout
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping
NB3N3001DTG
TSSOP8 4.4 mm
(Pb−Free)
100 Units / Rail
NB3N3001DTR2G
TSSOP8 4.4 mm
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
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