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부품번호 | NB3N551 기능 |
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기능 | Ultra-Low Skew 1:4 Clock Fanout Buffer | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 7 페이지수
NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin three−states the outputs when low.
Features
• Input/Output Clock Frequency up to 180 MHz
• Low Skew Outputs (50 ps typical)
• RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
• Output goes to Three−State Mode via OE
• Operating Range: VDD = 3.0 V to 5.5 V
• Ideal for Networking Clocks
• Packaged in 8−pin SOIC
• Industrial Temperature Range
• These are Pb−Free Devices
Q1
Q2
CLK
Q3
Q4
OE
Figure 1. Block Diagram
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8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
3N551
ALYW
G
1
3N551 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
DFN8
MN SUFFIX
1
CASE 506AA
14
6K = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
PIN CONNECTIONS
1
ICLK
Q1
2
3
Q2
Q3 4
8 OE
7
6
VDD
GND
5 Q4
ORDERING INFORMATION
Device
NB3N551DG
NB3N551DR2G
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Shipping†
98 Units/Rail
2500/Tape & Reel
NB3N551MNR4G DFN−8 1000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 4
1
Publication Order Number:
NB3N551/D
NB3N551
Table 5. DC CHARACTERISTICS (VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Min Typ
Max Unit
IDD
VOH
VOL
VOH
VIH, ICLK
VIL, ICLK
VIH, OE
VIL, OE
ZO
Power Supply Current @ 135 MHz, No Load, VDD = 3.3 V
Output HIGH Voltage – IOH = −25 mA, VDD = 3.3 V
Output LOW Voltage – IOL = 25 mA
Output HIGH Voltage – IOH = −12 mA (CMOS level)
Input HIGH Voltage, ICLK
Input LOW Voltage, ICLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
− 20 40 mA
2.4 −
−V
− − 0.4 V
VDD − 0.4
−
−V
(VDD/2)+0.7
−
3.8 V
−
−
(VDD/2)−0.7
V
2.0
−
VDD
V
0 − 0.8 V
− 20 − W
RPU
Input Pull−up Resistor, OE
− 220 − kW
CIN Input Capacitance, OE
− 5.0 − pF
IOS Short Circuit Current
− ± 50 − mA
DC CHARACTERISTICS (VDD = 4.5 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Min Typ Max Unit
IDD
VOH
VOL
VOH
VIH, ICLK
VIL, ICLK
VIH, OE
VIL, OE
ZO
Power Supply Current @ 135 MHz, No Load, VDD = 5.0 V
Output HIGH Voltage – IOH = −35 mA
Output LOW Voltage – IOL = 35 mA
Output HIGH Voltage – IOH = −12 mA (CMOS level)
Input HIGH Voltage, ICLK
Input LOW Voltage, ICLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
− 50 95 mA
2.4 −
−V
− − 0.4 V
VDD – 0.4
−
−V
(VDD/2) + 1
−
5.5 V
−
−
(VDD/2) − 1
V
2.0
−
VDD
V
0 − 0.8 V
− 20 − W
RPU
Input Pull−up Resistor, OE
− 220 − kW
CIN Input Capacitance, OE
− 5.0 − pF
IOS Short Circuit Current
− ±80
Table 6. AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Conditions
Min
Typ
− mA
Max Unit
fin Input Frequency
− − 180 MHz
tjitter (f) RMS Phase Jitter (Integrated 12 kHz − 20 MHz)
fcarrier = 25 MHz
−
43
− fs
(See Figures 2 and 3)
fcarrier = 50 MHz
−
16
−
tjitter (pd) Period Jitter (RMS, 1s)
− 2.0 − ps
tr/tf Output rise and fall times; 0.8 V to 2.0 V
− 0.5 1.0 ns
tpd Propagation Delay, CLK to Qn, 0 − 180 MHz,
(Note 4)
1.5 3.0 6.0 ns
tskew
Output−to−Output Skew; (Note 5)
− 50 160 ps
3. Outputs loaded with external RL = 33−W series resistor and CL = 15 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor
should be connected between VDD and GND. A 33 W series terminating resistor may be used on each clock output if the trace is longer than
1 inch.
4. Measured with rail−to−rail input clock.
5. Measured on rising edges at VDD ÷ 2.
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4
4페이지 NB3N551
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA−01
ISSUE E
DA
B
PIN ONE
REFERENCE
2X 0.10 C
ÇÇÇÇÇÇ
2X 0.10 C TOP VIEW
E
0.10 C
DETAIL B
0.08 C
NOTE 4
(A3)
A1
SIDE VIEW
LL
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
ÉÉÉÉEXPOSED Cu
MOLD CMPD
A DETAIL B
OPTIONAL
CONSTRUCTION
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.20 0.30
D 2.00 BSC
D2 1.10 1.30
E 2.00 BSC
E2 0.70 0.90
e 0.50 BSC
K 0.30 REF
L 0.25 0.35
L1 −−− 0.10
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
D2
14
8X L
PACKAGE
OUTLINE
1.30
8X
0.50
E2
K8
e/2
e
5 8X b
0.10 C A B
0.05 C NOTE 3
BOTTOM VIEW
0.90 2.30
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NB3N551/D
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