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PDF NB3N551 Data sheet ( Hoja de datos )
| Número de pieza | NB3N551 | |
| Descripción | Ultra-Low Skew 1:4 Clock Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin three−states the outputs when low.
Features
• Input/Output Clock Frequency up to 180 MHz
• Low Skew Outputs (50 ps typical)
• RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
• Output goes to Three−State Mode via OE
• Operating Range: VDD = 3.0 V to 5.5 V
• Ideal for Networking Clocks
• Packaged in 8−pin SOIC
• Industrial Temperature Range
• These are Pb−Free Devices
Q1
Q2
CLK
Q3
Q4
OE
Figure 1. Block Diagram
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
3N551
ALYW
G
1
3N551 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
DFN8
MN SUFFIX
1
CASE 506AA
14
6K = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
PIN CONNECTIONS
1
ICLK
Q1
2
3
Q2
Q3 4
8 OE
7
6
VDD
GND
5 Q4
ORDERING INFORMATION
Device
NB3N551DG
NB3N551DR2G
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Shipping†
98 Units/Rail
2500/Tape & Reel
NB3N551MNR4G DFN−8 1000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 4
1
Publication Order Number:
NB3N551/D
1 page  
NB3N551
Figure 2. Phase Noise Plot at 25 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3N551 device measured with an input
source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;
as shown in the shaded region of the plot) is 43 fs (RMS Jitter of the input source is 203.31 fs and Output (DUT+Source) is
247.06 fs).
Figure 3. Phase Noise Plot at 50 MHz at an Operating Voltage of 5 V, Room Temperature
The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3N551 device measured with an input
source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;
as shown in the shaded region of the plot) is 16 fs (RMS Jitter of the input source is 104.08 fs and Output (DUT + Source) is
119.77 fs).
http://onsemi.com
5
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