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PDF NB4N11M Data sheet ( Hoja de datos )
| Número de pieza | NB4N11M | |
| Descripción | Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator | |
| Fabricantes | ON Semiconductor | |
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NB4N11M
3.3 V 2.5 Gb/s Multi Level
Clock/Data Input to CML
Receiver/ Buffer/ Translator
Description
The NB4N11M is a differential 1−to−2 clock/data
distribution/translation chip with CML output structure, targeted for
high−speed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.
Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS
(See Table 5). The CML outputs are 16 mA open collector
(See Figure 18) which requires resistor (RL) load path to VTT
termination voltage. The open collector CML outputs must be
terminated to VTT at power up. Differential outputs produces
current–mode logic (CML) compatible levels when receiver loaded
with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies
(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.
The device is offered in a small 8−pin TSSOP package.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
• Maximum Input Clock Frequency > 2.5 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• Typically 1 ps of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 W
• 420 ps Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and
VTT = 1.8 V to 3.6 V
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• These are Pb−Free Devices*
http://onsemi.com
8
1
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAM*
8
E11M
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
D
D
Q1
Q1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 1
1
Publication Order Number:
NB4N11M/D
1 page  
NB4N11M
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V; (Note 8)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP
Output Voltage Amplitude (RL = 50 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.5GHz
550 660
400 640
150 400
550 660
400 640
150 400
550 660
400 640
150 400
mV
VOUTPP
Output Voltage Amplitude (RL = 25 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.5GHz
280 370
280 360
100 300
280 370
280 360
100 400
280 370
280 360
100 400
mV
fDATA
Maximum Operating Data Rate
1.5 2.5
1.5 2.5
1.5 2.5
Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential
@ 0.5 GHz
300 420 600 300 420 600 300 420 600 ps
tSKEW
Duty Cycle Skew (Note 9)
Within Device Skew
Device to Device Skew (Note 13)
2 20
5 25
20 100
2 20
5 25
20 100
2 20 ps
5 25
20 100
tJITTER
VINPP
RMS Random Clock Jitter RL = 50 W and
RL = 25 W (Note 11)
fin = 750 MHz
fin = 1.5 GHz
fin = 2.5 GHz
Peak−to−Peak Data Dependent Jitter RL = 50 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter RL = 25 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
1
1
1
15
20
5
10
100
31
31
31
55 15
85 20
35 5
35 10
100
31
31
31
55 15
85 20
35 5
35 10
100
ps
3
3
3
55
85
35
35
mV
tr Output Rise/Fall Times @ 0.5 GHz
tf (20% − 80%)
Q, Q
150 300
150 300
150 300 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All output loaded with an external RL = 50 W and RL = 25 W to VTT.
Outputs must be connected through RL to VTT at power up. Input edge rates 150 ps (20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
10. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12. Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 223−1).
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800 0.8
700 0.7
600
RL = 50 W
0.6 RL = 50 W
500 0.5
400
300 RL = 25 W
0.4
0.3 RL = 25 W
200 0.2
100 0.1
0
0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
INPUT CLOCK FREQUENCY (GHz)
(VCC − VEE = 3.3 V VTT = 3.3 V @ 255C Vin = 100 mV)
0
0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
INPUT CLOCK FREQUENCY (GHz)
(VCC − VEE = 3.0 V VTT = 1.71 V @255C Vin = 100 mV)
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
http://onsemi.com
5
5 Page 
NB4N11M
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
0.15 (0.006) T U S
2X L/2
L
PIN 1
IDENT
0.15 (0.006) T U S
8x K REF
0.10 (0.004) M T U S V S
85
B
1
−U−
4
A
−V−
0.25 (0.010)
M
F
DETAIL E
0.10 (0.004)
−T− SEATING
PLANE
D
C
G
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.80 1.10 0.031 0.043
D 0.05 0.15 0.002 0.006
F 0.40 0.70 0.016 0.028
G 0.65 BSC
0.026 BSC
K 0.25 0.40 0.010 0.016
L 4.90 BSC
0.193 BSC
M 0_ 6 _ 0_ 6_
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NB4N11M/D
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet NB4N11M.PDF ] | |
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