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PDF NB4N316M Data sheet ( Hoja de datos )
| Número de pieza | NB4N316M | |
| Descripción | AnyLevel Receiver to CML Driver/Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB4N316M
3.3 V AnyLevelt Receiver
to CML Driver/Translator
with Input Hysteresis
2.0 GHz Clock / 2.5 Gb/s Data
The NB4N316M is a differential Clock or Data receiver and will
accept AnyLevelt input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to CML, operating
up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is
ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or
Data distribution applications. The CML outputs are 16 mA open
collector (see Figure 18) which requires resistor (RL) load path to VTT
termination voltage (see Figure 19). The open collector CML outputs
must be terminated to VTT at power up. The differential outputs
produce Current–Mode Logic (CML) compatible levels when the
receiver is loaded with 50 W or 25 W loads connected to 1.8 V, 2.5 V
or 3.3 V supplies. This simplifies device interface by eliminating a
need for coupling capacitors.
The NB4N316M features an input threshold hysteresis of
approximately 25 mV, providing increased noise immunity and stability.
The device is offered in a small 8−pin TSSOP package (MSOP−8
compatible). Application notes, models, and support documentation
are available at www.onsemi.com.
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• Typically 1 ps of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 550 ps Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• Differential CML Outputs
• 25 mV of Receiver Input Threshold Hysteresis
• Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and
VTT = 1.8 V to 3.6 V
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL,
LVEP, EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices*
http://onsemi.com
8
1
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAM*
8
E316
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
DQ
DQ
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 3
1
Publication Order Number:
NB4N316M/D
1 page  
NB4N316M
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V; (Note 8)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP
VOUTPP
fDATA
tPLH,
tPHL
tSKEW
Output Voltage Amplitude (RL = 50 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
Output Voltage Amplitude (RL = 25 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
Maximum Operating Data Rate
Propagation Delay to Output Differential
@ 0.25 GHz
Duty Cycle Skew (Note 9)
Device to Device Skew (Note 13)
550 660
400 640
200 400
550 660
400 640
200 400
550 660
400 640
200 400
mV
280 370
280 360
200 300
280 370
280 360
200 400
280 370
280 360
200 400
mV
1.5 2.5
1.5 2.5
1.5 2.5
Gb/s
350 550 750 350 550 750 350 550 750 ps
2 20
20 100
2 20
20 100
2 20 ps
20 100
tJITTER
VINPP
RMS Random Clock Jitter RL = 50 W and
RL = 25 W (Note 11)
fin = 750 MHz
fin = 1.5 GHz
fin = 2.0 GHz
Peak−to−Peak Data Dependent Jitter RL = 50 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter RL = 25 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
1
1
1
15
20
5
10
200
31
31
31
55 15
85 20
35 5
35 10
200
31
31
31
55 15
85 20
35 5
35 10
200
ps
3
3
3
55
85
35
35
mV
tr Output Rise/Fall Times @ 0.25 GHz Q, Q
tf (20% − 80%)
150 300
150 300
150 300 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All output loaded with an external RL = 50 W and RL = 25 W to VTT.
Outputs must be connected through RL to VTT at power up. Input edge rates 150 ps (20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.25 GHz.
10. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12. Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 223−1).
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800 0.8
700
600 RL = 50 W
0.7 RL = 50 W
0.6
500 0.5
400
300 RL = 25 W
0.4
0.3 RL = 25 W
200 0.2
100 0.1
0
0.5 0.75 1 1.25 1.5 1.75 2
INPUT CLOCK FREQUENCY (GHz)
(VCC − VEE = 3.3 V VTT = 3.3 V @ 255C Vin = 100 mV)
0
0.5 0.75 1 1.25 1.5 1.75 2
INPUT CLOCK FREQUENCY (GHz)
(VCC − VEE = 3.0 V VTT = 1.71 V @255C Vin = 100 mV)
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
http://onsemi.com
5
5 Page 
NB4N316M
ORDERING INFORMATION
Device
Package
Shipping†
NB4N316MDTG
TSSOP−8
(Pb−Free)
100 Units / Rail
NB4N316MDTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
http://onsemi.com
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NB4N316M.PDF ] | |
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