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PDF NB4N840M Data sheet ( Hoja de datos )
| Número de pieza | NB4N840M | |
| Descripción | 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch | |
| Fabricantes | ON Semiconductor | |
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NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
The NB4N840M is a high−bandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loop−through and protection channel switching
applications.
Internally terminated differential CML inputs accept AC−coupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50 W input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50 W terminations, and 400 mV output swings when
externally terminated, 50 W to VCC.
Single−ended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32−pin QFN package.
Features
• Plug−in compatible to the MAX3840 and SY55859L
• Maximum Input Clock Frequency 2.7 GHz
• Maximum Input Data Frequency 3.2 Gb/s
• 225 ps Typical Propagation Delay
• 80 ps Typical Rise and Fall Times
• 7 ps Channel to Channel Skew
• 430 mW Power Consumption
• < 0.5 ps RMS Jitter
• 7 ps Peak−to−Peak Data Dependent Jitter
• Power Saving Feature with Disabled Outputs
• Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output), Differential
Output
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB4N
840M
ALYWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
DA0
DA0
CML
DA1
DA1
CML
DB0
DB0
CML
0
CML
1
0
CML
1
0
CML
1
QA0
QA0
ENA0
SELA0
QA1
QA1
ENA1
SELA1
QB0
QB0
ENB0
SELB0
DB1
DB1
CML
0
CML
1
QB1
QB1
ENB1
SELB1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 5
1
Publication Order Number:
NB4N840M/D
1 page  
NB4N840M
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 3.0 V to 3.6 V, TA = −40°C to +85°C
Symbol
Characteristic
Min Typ Max
Unit
ICC
Voutdiff
VCMR
(Note 6)
Power Supply Current (All outputs enabled)
CML Differential Output Swing (Note 4, Figures 5 and 12)
CML Output Common Mode Voltage (Loaded 50 W to VCC)
CML Single−Ended Input Voltage Range
VID Differential Input Voltage (VIHD − VILD)
LVTTL CONTROL INPUT PINS
130 170
640 800 1000
VCC − 800
300
VCC − 200
VCC + 400
1600
mA
mV
mV
mV
mV
VIH
VIL
IIH
IIL
RTIN
RTOUT
Input HIGH Voltage (LVTTL Inputs)
Input LOW Voltage (LVTTL Inputs)
Input HIGH Current (LVTTL Inputs)
Input LOW Current (LVTTL Inputs)
CML Single−Ended Input Resistance
Differential Output Resistance
2000
mV
800 mV
−10 10 mA
−10 10 mA
42.5 50 57.5 W
85 100 115 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs require 50 W receiver termination resistors to VCC for proper operation (Figure 10).
5. Input and output parameters vary 1:1 with VCC.
6. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V (Note 7, Figure 9)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP
Output Voltage Amplitude (@ VINPPmin) fin ≤ 2 GHz
(See Figure 3)
fin ≤ 3 GHz
fin ≤ 3.5 GHz
280
235
170
365
310
220
280 365
235 310
170 220
280 365
235 310
170 220
mV
fDATA
tPLH,
tPHL
Maximum Operating Data Rate
3.2 3.2 3.2 Gb/s
Propagation Delay to Output Differential
ps
D/D to Q/Q 140 225 340 140 225 340 140 225 340
tSKEW
Duty Cycle Skew (Note 8)
Within−Device Skew (Figure 4)
Device−to−Device Skew (Note 12)
5 25
5 25
20 85
5 25
5 25
20 85
5 25 ps
5 25
20 85
tJITTER
RMS Random Clock Jitter (Note 10) fin v 3.2 GHz
Peak−to−Peak Data Dependent Jitter fin = 2.5 Gb/s
(Note 11)
fin = 3.2 Gb/s
Crosstalk−Induced RMS Jitter (Note 13)
0.15 0.5
7 20
7 20
0.5
0.15 0.5
7 20
7 20
0.5
0.15 0.5
7 20
7 20
0.5
ps
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 9)
150
800 150
800 150
800 mV
tr Output Rise/Fall Times @ 0.5 GHz
tf (20% − 80%)
Q, Q
80 135
80 135
80 135 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
9. VINPP (MAX) cannot exceed 800 mV. Input voltage swing is a single−ended measurement operating in differential mode.
10. Additive RMS jitter using 50% duty cycle clock input signal.
11. Additive peak−to−peak data dependent jitter using input data pattern with PRBS 223−1 and K28.5, VINPP = 400 mV.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Data taken on the same device under identical condition.
http://onsemi.com
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