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PDF NB6L11M Data sheet ( Hoja de datos )
| Número de pieza | NB6L11M | |
| Descripción | Differential CML Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB6L11M
2.5V / 3.3V 1:2 Differential
CML Fanout Buffer
Multi−Level Inputs w/ Internal Termination
Description
The NB6L11M is a differential 1:2 CML fanout buffer. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pins and will accept LVPECL, LVCMOS,
LVTTL, CML, or LVDS logic levels.
The VREFAC pin is an internally generated voltage supply available
to this device only. VREFAC is used as a reference voltage for
single−ended PECL or NECL inputs. For all single−ended input
conditions, the unused complementary differential input is connected
to VREFAC as a switching reference voltage. VREFAC may also rebias
capacitor−coupled inputs. When used, decouple VREFAC with a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VREFAC output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L11M is a member of the ECLinPS MAXt family of
high performance clock products.
Features
• Maximum Input Clock Frequency > 4 GHz, Typical
• 225 ps Typical Propagation Delay
• 70 ps Typical Rise and Fall Times
• 0.5 ps maximum RMS Clock Jitter
• Differential CML Outputs, 380 mV peak−to−peak, typical
• LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V
• NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V
• Internal Input Termination Resistors, 50 W
• VREFAC Reference Output
• Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP,
EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
11M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
VREFAC
Q0
Q0
Q1
Q1
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page NO TAG of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 0
1
Publication Order Number:
NB6L11M/D
1 page  
NB6L11M
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to
+85°C; (Note 10)
Symbol
Characteristic
Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPP(MIN)
(Note 15) (See Figure 9)
tPD
tSKEW
Propagation Delay
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
fin ≤ 3.0GHz
fin ≤ 3.5 GHz
fin ≤ 4.0 GHz
D to Q
230 380
190 320
150 270
mV
175 225 325 ps
5.0 15 ps
3.0 15
80
tDC
tJITTER
VINPP
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
RMS Random Clock Jitter (Note 13)
Peak−to−Peak Data Dependent Jitter
(Note 14)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
fin ≤ 4.0GHz
fin ≤ 4GHz
fin ≤ 4Gb/s
40 50 60 %
ps
0.2 0.5
40
150
2800
mV
tr Output Rise/Fall Times @ 0.5 GHz
tf (20% − 80%)
Q, Q
70 120 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
http://onsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet NB6L11M.PDF ] | |
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