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PDF NB6L14 Data sheet ( Hoja de datos )
| Número de pieza | NB6L14 | |
| Descripción | Differential 1:4 LVPECL Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB6L14
2.5 V/3.3 V 3.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
Multi−Level Inputs with Internal Termination
Description
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL fanout buffer.
The differential inputs incorporate internal 50 W termination resistors
that are accessed through the VT pin. This feature allows the NB6L14
to accept various logic standards, such as LVPECL, LVCMOS,
LVTTL, CML, or LVDS logic levels. The VREF_AC reference output
can be used to rebias capacitor−coupled differential or single−ended
input signals. The 1:4 fanout design was optimized for low output
skew applications.
The NB6L14 is a member of the ECLinPS MAX™ family of high
performance clock and data products.
Features
• Maximum Input Clock Frequency > 2.5 GHz, Typical
• < 20 ps Within Device Output Skew
• 330 ps Typical Propagation Delay
• 145 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 720 mV Amplitude, Typical
• LVPECL Mode Operating Range: VCC = 2.375 V to 3.63 V with
GND = 0 V
• Internal 50 W Input Termination Resistors Provided
• VREF_AC Reference Output Voltage
• −40°C to +85°C Ambient Operating Temperature
• Available in 3 mm x 3 mm 16 Pin QFN
• These are Pb−Free Devices
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
DQ
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 0
1
Publication Order Number:
NB6L14/D
1 page  
NB6L14
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = −40°C to +85°C (Note 9)
Symbol
Characteristic
Min Typ
VOUTPP
tPD
tS
tH
tSKEW
Output Voltage Amplitude (@ VINPPmin) (Note 10)
≤ 1.25 GHz
1.25 GHz ≤ fin ≤ 2.0 GHz
2.0 GHz ≤ fin ≤ 3.0 GHz
Propagation Delay
IN to Q
Set−Up Time (Note 11)
EN to IN, IN
Hold Time (Note 11)
EN to IN, IN
Within−Device Skew (Note 12)
Device to Device Skew (Note 13)
550
380
250
300
300
700
500
320
350
5.0
tJITTER
VINPP
RMS Random Jitter (Note 14)
Peak−to−Peak Data Dependent Jitter
(Note 15)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
fIN = 2.5 GHz
fIN = 2.5 Gb/s
100
14
tr,tf Output Rise/Fall Times @ Full Output Swing
(20%−80%)
70 150
Max
20
150
1.0
2800
200
Unit
mV
ps
ps
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPP (min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge rates
40 ps (20%−80%).
10. Input and output voltage swing is a single−ended measurement operating in differential mode.
11. Set−up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set−up and hold times do not apply.
12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions.
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2^23−1 and K28.5 at 2.5Gb/s.
http://onsemi.com
5
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