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NB6L611 데이터시트 PDF




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부품번호 NB6L611 기능
기능 Differential LVPECL Clock / Data Fanout Buffer
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NB6L611 데이터시트, 핀배열, 회로
www.DataSheet4U.com
NB6L611
2.5V / 3.3V 1:2 Differential
LVPECL Clock / Data Fanout
Buffer
MultiLevel Inputs with Internal Termination
http://onsemi.com
Description
The NB6L611 is a differential 1:2 fanout buffer. The differential
inputs incorporate internal 50 W termination resistors that are accessed
through the VTD pins and will accept LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels.
The VREFAC pin is an internally generated voltage supply available
to this device only. VREFAC is used as a reference voltage for
singleended PECL or NECL inputs. For all singleended input
conditions, the unused complementary differential input is connected
to VREFAC as a switching reference voltage. VREFAC may also rebias
capacitorcoupled inputs. When used, decouple VREFAC with a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VREFAC output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L611 is a member of the ECLinPS MAXfamily of high
performance clock products.
Features
Maximum Input Clock Frequency > 4.0 GHz, Typical
280 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential LVPECL Outputs, 780 mV Amplitude, typical
LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V
NECL Operating Range: VCC = 0 V with VEE = 2.375 V to 3.63 V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output Voltage
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
611
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
Q0
Q0
Q1
Q1
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 Rev. 0
1
Publication Order Number:
NB6L611/D




NB6L611 pdf, 반도체, 판매, 대치품
NB6L611
Table 4. DC CHARACTERISTICS, MultiLevel Inputs VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = 2.375 V to
3.63 V, TA = 40°C to +85°C
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY CURRENT
ICC Power Supply Current (Inputs and Outputs Open)
LVPECL OUTPUTS (Notes 4 and 5)
30 45 60 mA
VOH Output HIGH Voltage
VCC = 3.3 V
VCC = 2.5 V
VCC 1075
2225
1425
VCC 950
2350
1550
VCC 825
2475
1675
mV
VOL Output LOW Voltage
VCC = 3.3V
VCC = 2.5V
VCC 1875
1475
675
DIFFERENTIAL INPUT DRIVEN SINGLEENDED (see Figures 4 and 5) (Note 6)
VCC 1725
1575
775
VCC 1625
1675
875
mV
Vth Input Threshold Reference Voltage Range (Note 7)
VEE + 1125
VIH Singleended Input HIGH Voltage
Vth + 75
VIL Singleended Input LOW Voltage
VEE
VISE
Singleended Input Voltage Amplitude (VIH VIL)
150
VREFAC
VREFAC Output Reference Voltage
VCC – 1.525
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6, 7 and 8) (Note 8)
VCC – 1.425
VCC 75
VCC
Vth 75
2800
VCC – 1.325
mV
mV
mV
mV
mV
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
VID Differential Input Voltage (VIHD VILD)
VCMR
Input Common Mode Range (Differential Configuration) (Note9)
IIH Input HIGH Current D/D, (VTD/VTD Open)
IIL Input LOW Current D/D, (VTD/VTD Open)
TERMINATION RESISTORS
VEE + 1200
VEE
VEE + 150
VEE + 1125
10
50
VCC
VCC 150
2800
VCC 75
50
10
mV
mV
mV
mV
mA
mA
RTIN
Internal Input Termination Resistor (Measured from D to VTD)
40 50 60 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50 W to VCC 2.0 V for proper operation.
5. Input and output parameters vary 1:1 with VCC.
6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
7. Vth is applied to the complementary input when operating in singleended mode.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
9. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the
differential input signal.
http://onsemi.com
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NB6L611 전자부품, 판매, 대치품
NB6L611
VCC
VCC
VCC
VCC
LVPECL
Driver
ZO = 50 W
VT
ZO =
=50VWCC
2
V
NB6L611
D
50 W
50 W
D
VEE
VEE
Figure 10. LVPECL Interface
LVDS
Driver
ZO = 50 W
ZO
=
5V0T
=
W
Open
NB6L611
D
50 W
50 W
D
VEE
VEE
Figure 11. LVDS Interface
VCC
VCC
CML
Driver
ZO = 50 W
ZO
=
50
VT
W
=
VCC
NB6L611
D
50 W
50 W
D
VEE
VEE
Figure 12. Standard 50 W Load CML Interface
VCC
VCC
VCC
VCC
Differential
Driver
ZO = 50 W
ZO
VT =
= 50
VREFAC*
W
NB6L611
D
50 W
50 W
D
VEE
Figure 13. CapacitorCoupled
Differential Interface
(VT Connected to VREFAC)
VEE
*VREFAC bypassed to ground with a 0.01 mF capacitor
SingleEnded
Driver
ZO = 50 W
VT = VREFAC*
NB6L611
D
50 W
50 W
D (Open)
VEE
Figure 14. CapacitorCoupled
SingleEnded Interface
(VT Connected to VREFAC)
VEE
http://onsemi.com
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부품번호상세설명 및 기능제조사
NB6L611

Differential LVPECL Clock / Data Fanout Buffer

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