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ATR0630 데이터시트 PDF




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부품번호 ATR0630 기능
기능 Single-chip GPS Receiver
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ATR0630 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features
16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –139 dBm (With External LNA)
– Tracking Sensitivity: –149 dBm (With External LNA)
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– Embedded ICE (In-Circuit Emulation)
128 Kbytes Internal RAM
384 Kbytes Internal ROM with u-blox GPS Firmware
1.5-bit ADC On-chip
Single IF Architecture
2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
2 USARTs
Master/Slave SPI Interface
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
4 KBytes of Battery Backup Memory
7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
Benefits
Fully Integrated Design With Low BOM
No External Flash Memory Required
Requires Only a GPS XTAL, No TCXO
Supports NMEA, UBX Binary and RTCM Protocol
Supports SBAS (WAAS, EGNOS, MSAS)
Up to 4Hz Update Rate
Supports A-GPS (Aiding)
Excellent Noise Performance
ANTARIS4
Single-chip
GPS Receiver
ATR0630
Preliminary
Rev. 4920A–GPS–01/06




ATR0630 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
2.2 General Description
The ATR0630 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0630 is based on the successful ANTARIS4 technology which includes the ANTARIS ROM
software, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation engine
which is used in high-end car navigation systems, automatic vehicle location (AVL), security and
surveying systems, traffic control, road pricing, and speed camera detectors, and provides loca-
tion-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Especially, due to its fast search engine and GPS accelerator, the
ATR0630 only needs a GPS crystal (XTAL) as a resonator for the integrated crystal oscillator of
the ATR0630. This saves the considerable higher cost of a TCXO which is required for competi-
tor’s systems. Also, as the powerful standard software is available in ROM, no external flash
memory is needed.
The L input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-
quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
2.3 PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
2.4 XTO
The XTO is designed for minimum phase noise and frequency perturbations. The balanced
topology gives maximum isolation from external and ground coupled noise. The built-in jump
start circuitry ensures reliable start-up behavior of any specified crystal. For use with an external
TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.
The recommended reference frequency is: fXTO = 23.104 MHz.
2.5 VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression. The relation between the reference frequency (fXTO) and the
VCO center frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
2.6 RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
4 ATR0630 [Preliminary]
4920A–GPS–01/06

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ATR0630 전자부품, 판매, 대치품
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ATR0630 [Preliminary]
Table 3-1. ATR0630 Pinout (Continued)
Pin Name BGA 96
Pin Type
Pull Resistor
(Reset Value)(1)
Firmware Label
PIO Bank A
I
O
GNDA
B4
Supply
GNDA
D2
Supply
GNDA
E1
Supply
GNDA
E2
Supply
GNDA
E3
Supply
GNDA
F1
Supply
GNDA
F2
Supply
GNDA
F3
Supply
GNDA
G1
Supply
GNDA
H1
Supply
LDOBAT_IN D11
Supply
LDO_EN C11
Digital IN
LDO_IN E11
Supply
LDO_OUT E12
Supply
MO C3 Analog OUT
NRESET
A7
Digital I/O
Open Drain PU
NRF C1 Analog IN
NSHDN
E9
Digital OUT
NSLEEP E10
Digital OUT
NTRST
H11
Digital IN
PD
NX B2 Analog OUT
NXTO
B3
Analog IN
P0 C8 Digital I/O
PD
NANTSHORT
P1 D8 Digital I/O Configurable (PD) GPSMODE0
P2 C6 Digital I/O Configurable (PD) BOOT_MODE
‘0’
P8 D7 Digital I/O Configurable (PD) STATUSLED
‘0’
P9 A11 Digital I/O
PU
EXTINT0
EXTINT0
P12 D6 Digital I/O Configurable (PU)
GPSMODE2
NPCS2
P13 B10 Digital I/O
PU
GPSMODE3
EXTINT1
P14 G6 Digital I/O Configurable (PD)
NAADET1
‘0’
P15 F11 Digital I/O
PD
ANTON
P16 G8 Digital I/O Configurable (PU)
NEEPROM
P17 H6 Digital I/O Configurable (PD) GPSMODE5
SCK1
SCK1
P18 C7 Digital I/O Configurable (PU)
TXD1
TXD1
P19 F6 Digital I/O Configurable (PU) GPSMODE6
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
4920A–GPS–01/06
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