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PDF AD2S1205 Data sheet ( Hoja de datos )
| Número de pieza | AD2S1205 | |
| Descripción | 12-Bit RDC | |
| Fabricantes | Analog Devices | |
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FEATURES
Complete monolithic resolver-to-digital converter (RDC)
Parallel and serial 12-bit data ports
System fault detection
±11 arc minutes of accuracy
Input signal range: 3.15 V p-p ± 27%
Absolute position and velocity outputs
1250 rps maximum tracking rate, 12-bit resolution
Incremental encoder emulation (1024 pulses/rev)
Programmable sinusoidal oscillator on board
Single-supply operation (5.00 V ± 5%)
−40°C to +125°C temperature rating
44-lead LQFP
4 kV ESD protection
Qualified for automotive applications
APPLICATIONS
Automotive motion sensing and control
Hybrid-electric vehicles
Electric power steering
Integrated starter generator/alternator
Industrial motor control
Process control
GENERAL DESCRIPTION
The AD2S1205 is a complete 12-bit resolution tracking
resolver-to-digital converter that contains an on-board
programmable sinusoidal oscillator providing sine wave
excitation for resolvers.
The converter accepts 3.15 V p-p ± 27% input signals on the Sin
and Cos inputs. A Type II tracking loop is employed to track the
inputs and convert the input Sin and Cos information into a digital
representation of the input angle and velocity. The maximum
tracking rate is a function of the external clock frequency. The
performance of the AD2S105 is specified across a frequency
range of 8.192 MHz ± 25%, allowing a maximum tracking rate
of 1250 rps.
12-Bit RDC
with Reference Oscillator
AD2S1205
EXCITATION
OUTPUTS
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
PINS
CRYSTAL
AD2S1205
REFERENCE
OSCILLATOR
(DAC)
VOLTAGE
REFERENCE
INTERNAL
CLOCK
GENERATOR
SYNTHETIC
REFERENCE
INPUTS
FROM
RESOLVER
ADC
ADC
TYPE II TRACKING LOOP
FAULT
DETECTION
ENCODER
EMULATION
OUTPUTS
POSITION REGISTER VELOCITY REGISTER
ENCODER
EMULATION
MULTIPLEXER
DATA BUS OUTPUT
FAULT
DETECTION
OUTPUTS
RESET
DATA I/O
Figure 1.
PRODUCT HIGHLIGHTS
1. Ratiometric Tracking Conversion. The Type II tracking
loop provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
2. System Fault Detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking.
3. Input Signal Range. The Sin and Cos inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
4. Programmable Excitation Frequency. Excitation frequency
is easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz
by using the frequency select pins (the FS1 and FS2 pins).
5. Triple Format Position Data. Absolute 12-bit angular position
data is accessed via either a 12-bit parallel port or a 3-wire
serial interface. Incremental encoder emulation is in standard
A-quad-B format with direction output available.
6. Digital Velocity Output. 12-bit signed digital velocity accessed
via either a 12-bit parallel port or a 3-wire serial interface.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage (VDD)
Supply Voltage (AVDD)
Input Voltage
Output Voltage Swing
Input Current to Any Pin Except Supplies1
Operating Temperature Range (Ambient)
Storage Temperature Range
Rating
−0.3 V to +7.0 V
−0.3 V to +7.0 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
±10 mA
−40°C to +125°C
−65°C to +150°C
1 Transient currents of up to 100 mA do not cause latch-up.
AD2S1205
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 20
5 Page 
AD2S1205
ON-BOARD PROGRAMMABLE SINUSOIDAL
OSCILLATOR
An on-board oscillator provides the sinusoidal excitation signal
(EXC) and its complement signal (EXC) to the resolver. The fre-
quency of this reference signal is programmable to four standard
frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) by using the
FS1 and FS2 pins (see Table 5). FS1 and FS2 have internal pull-ups,
so the default frequency is 10 kHz. The amplitude of this signal
is centered on 2.5 V and has an amplitude of 3.6 V p-p.
Table 5. Excitation Frequency Selection
Frequency Selection (kHz)
FS1
10 1
12 1
15 0
20 0
FS2
1
0
1
0
The frequency of the reference signal is a function of the CLKIN
frequency. By decreasing the CLKIN frequency, the minimum
excitation frequency can also be decreased. This allows an
excitation frequency of 7.5 kHz to be set when using a CLKIN
frequency of 6.144 MHz, and it also decreases the maximum
tracking rate to 750 rps.
The reference output of the AD2S1205 requires an external buffer
amplifier to provide gain and additional current to drive the
resolver. See Figure 6 for a suggested buffer circuit.
The AD2S1205 also provides an internal synchronous reference
signal that is phase locked to its Sin and Cos inputs. Phase errors
between the resolver’s primary and secondary windings may
degrade the accuracy of the RDC and are compensated for by using
this synchronous reference signal. This also compensates for the
phase shifts due to temperature and cabling, and it eliminates the
need for an external preset phase-compensation circuit.
SYNTHETIC REFERENCE GENERATION
When a resolver undergoes a high rotation rate, the RDC tends
to act as an electric motor and produces speed voltages in
addition to the ideal Sin and Cos outputs. These speed voltages are
in quadrature to the main signal waveform. Moreover, nonzero
resistance in the resolver windings causes a nonzero phase shift
between the reference input and the Sin and Cos outputs. The
combination of the speed voltages and the phase shift causes a
tracking error in the RDC that is approximated by
Error = Phase Shift × RotationRate
Reference Frequency
(6)
To compensate for the described phase error between the resolver
reference excitation and the Sin/Cos signals, an internal synthetic
reference signal is generated in phase with the reference frequency
carrier. The synthetic reference is derived using the internally
filtered Sin and Cos signals. It is generated by determining the
zero crossing of either the Sin or Cos (whichever signal is
larger), which improves phase accuracy, and evaluating the phase
of the resolver reference excitation. The synthetic reference reduces
the phase shift between the reference and Sin/Cos inputs to less
than 10° and can operate for phase shifts of ±45°.
CHARGE-PUMP OUTPUT
A 204.8 kHz square wave output with a 50% duty cycle is available
at the CPO pin of the AD2S1205. This square wave output can
be used for negative rail voltage generation or to create a VCC rail.
CONNECTING THE CONVERTER
Ground is connected to the AGND and DGND pins (see Figure 5).
A positive power supply (VDD) of 5 V dc ± 5% is connected to
the AVDD and DVDD pins, with typical values for the decoupling
capacitors being 10 nF and 4.7 μF. These capacitors are then
placed as close to the device pins as possible and are connected
to both AVDD and DVDD. If desired, the reference oscillator
frequency can be changed from the nominal value of 10 kHz
using FS1 and FS2. Typical values for the oscillator decoupling
capacitors are 20 pF, whereas typical values for the reference
decoupling capacitors are 10 μF and 0.01 μF. As outlined in the
Loss of Signal Detection section 68 kΩ resistors between the Sin
and SinLO inputs and the Cos and CosLO inputs can be used to
ensure loss of signal detection when all four inputs from resolver
are disconnected.
In this recommended configuration, the converter introduces a
VREF/2 offset in the Sin and Cos signal outputs from the resolver.
The SinLO and CosLO signals can each be connected to a different
potential relative to ground if the Sin and Cos signals adhere to the
recommended specifications. Note that because the EXC and EXC
outputs are differential, there is an inherent gain of 2×. Figure 6
shows a suggested buffer circuit. Capacitor C1 may be used in
parallel with Resistor R2 to filter out any noise that may exist on the
EXC and EXC outputs. Care should be taken when selecting the
cutoff frequency of this filter to ensure that phase shifts of the
carrier caused by the filter do not exceed the phase lock range
of the AD2S1205.
The gain of the circuit is
CarrierGain = − (R2 / R1)×(1/(1+ R2×C1×ω))
(7)
and
VOUT
=
⎜⎝⎛VREF
×
⎜⎛1
⎝
+
R2⎟⎞⎟⎞
R1⎠⎠
−
⎜⎛
⎝
R2
R1
×(1/(1
+
R2×C1×
ω))VIN
⎟⎞
⎠
(8)
where:
ω is the radian frequency of the applied signal.
VREF, a dc voltage, is set so that VOUT is always a positive value,
eliminating the need for a negative supply.
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD2S1205.PDF ] | |
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