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부품번호 | AD6624 기능 |
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기능 | 80 MSPS Digital Receive Signal Processor | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 30 페이지수
www.DataSheet4U.com
a
Four-Channel, 80 MSPS Digital
Receive Signal Processor (RSP)
FEATURES
80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI)
Dual High Speed Data Input Ports
Four Independent Digital Receivers in Single Package
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User-Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136,
EDGE, PHS, IS95
Micro and Pico Cell Systems
Wireless Local Loop
Smart Antenna Systems
Software Radios
In-Building Wireless Telephony
PRODUCT DESCRIPTION
The AD6624 is a four-channel (quad) digital receive signal
processor (RSP) with four cascaded signal-processing elements:
a frequency translator, two fixed-coefficient decimating filters,
and a programmable-coefficient decimating filter.
AD6624
The AD6624 is part of Analog Devices’ SoftCell® multicarrier
transceiver chipset designed for compatibility with Analog
Devices’ family of high sample rate IF sampling ADCs (AD6640/
AD6644 12- and 14-bit). The SoftCell receiver comprises a
digital receiver capable of digitizing an entire spectrum of
carriers and digitally selecting the carrier of interest for tuning
and channel selection. This architecture eliminates redundant
radios in wireless base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 30 dB or more. In addition, the programmable RAM
coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The AD6624 is compatible with standard ADC converters such
as the AD664x, AD9042, AD943x, and the AD922x families of
data converters. The AD6624 is also compatible with the AD6600
Diversity ADC, providing a cost and size reduction path.
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
SYNCA
SYNCB
SYNCC
SYNCD
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
CH A
FUNCTIONAL BLOCK DIAGRAM
NCO
16 BITS
18 BITS
rCIC2
RESAMPLER
CIC5
20 BITS
24 BITS
RAM
COEFFICIENT
FILTER
CH B
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH C
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH D
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
SDIN[3:0]
SDO[3:0]
DR[3:0]
SDFS[3:0]
SDFE[3:0]
SCLK[3:0]
MODE
DS(RD)
CS
RW (WR)
DTACK(RDY)
A[2:0]
D[7:0]
EXTERNAL SYNC
CIRCUITRY
JTAG
INTERFACE
BUILT-IN
SELF-TEST
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
AD6624–SPECIFICATIONS
GENERAL TIMING CHARACTERISTICS1, 2
Parameter (Conditions)
Test AD6624AS
Temp Level Min Typ
Max Unit
CLK Timing Requirements:
tCLK
tCLKL
tCLKH
CLK Period
CLK Width Low
CLK Width High
Full I
Full IV
Full IV
12.5
4.5
4.5
0.5 × tCLK
0.5 × tCLK
ns
ns
ns
RESET Timing Requirement:
tRESL
RESET Width Low
Full I
30.0
ns
Input Wideband Data Timing Requirements:
tSI Input to ↑CLK Setup Time
tHI Input to ↑CLK Hold Time
Full IV
Full IV
0.8
2.0
ns
ns
Level Indicator Output Switching Characteristic:
tDLI ↑CLK to LI (A–A, B; B–A, B) Output Delay Time
Full IV
3.8
12.6 ns
SYNC Timing Requirements:
tSS SYNC (A, B, C, D) to ↑CLK Setup Time
tHS SYNC (A, B, C, D) to ↑CLK Hold Time
Full IV
Full IV
1.0
2.0
ns
ns
Serial Port Timing Requirements (SBM = 1):
Switching Characteristics:3
tDSCLK1
tDSCLKH
tDSCLKL
tDSCLKLL
tDSDFS
tDSDFE
tDSDO
tDSDR
tDDR
↑CLK to ↑SCLK Delay (Divide by 1)
↑CLK to ↑SCLK Delay (For Any Other Divisor)
↑CLK to ↓SCLK Delay (Divide by 2 or Even #)
↓CLK to ↓SCLK Delay (Divide by 3 or Odd #)
↑SCLK to SDFS Delay
↑SCLK to SDFE Delay
↑SCLK to SDO Delay
↑SCLK to DR Delay
↑CLK to DR Delay
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
3.9
4.4
3.25
3.8
0.2
–0.4
–1.0
–0.3
5.4
13.4 ns
14.0 ns
6.7 ns
6.9 ns
5.3 ns
+4.7 ns
+4.0 ns
+4.6 ns
17.6 ns
Input Characteristics:
tSSI SDI to ↓SCLK Setup Time
tHSI SDI to ↓SCLK Hold Time
Full IV
Full IV
2.4
3.0
ns
ns
Serial Port Timing Requirements (SBM = 0):
Switching Characteristics:3
tSCLK
tSCLKL
tSCLKH
tDSDFE
tDSDO
tDSDR
SCLK Period
SCLK Low Time (When SDIV = 1, Divide by 1)
SCLK High Time (When SDIV = 1, Divide by 1)
↑SCLK to SDFE Delay
↑SCLK to SDO Delay
↑SCLK to DR Delay
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
16
5.0
5.0
3.8
3.7
3.9
ns
ns
ns
15.4 ns
15.2 ns
15.9 ns
Input Characteristics:
tSSF SDFS to ↑SCLK Setup Time
tHSF SDFS to ↑SCLK Hold Time
tSSI SDI to ↓SCLK Setup Time
tHSI SDI to ↓SCLK Hold Time
Full IV
Full IV
Full IV
Full IV
1.9
0.7
2.4
2.0
ns
ns
ns
ns
NOTES
1All timing specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2CLOAD = 40 pF on all outputs unless otherwise specified.
3The timing parameters for SCLK, SDFS, SDFE, SDO, SDI, and DR apply to all four channels (0, 1, 2, and 3). The slave serial port’s (SCLK) operating frequency is
limited to 62.5 MHz.
Specifications subject to change without notice.
–4– REV. B
4페이지 SCLK
tDSDO
tDSDFE
SDO
I15 I14
Q1 Q0
SDFE
Figure 8. SDO, SDFE Switching Characteristics
AD6624
SCLK
SDFS
tSSF
tHSF
Figure 11. SDFS Timing Requirements (SBM = 0)
CLK
tDDR
DR
Figure 9. CLK, DR Switching Characteristics
CLK
tSI tHI
IN[13:0]
EXP[2:0]
IEN
Figure 12. Input Timing for A and B Channels
SCLK
DR
tDSDR
Figure 10. SCLK, DR Switching Characteristics
CLK
SYNCA
SYNCB
SYNCC
SYNCD
tSS tHS
Figure 13. SYNC Timing Inputs
REV. B
–7–
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |