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부품번호 AD7327 기능
기능 12-Bit Plus Sign ADC
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AD7327 데이터시트, 핀배열, 회로
www.DataSheet4U.com
500 kSPS, 8-Channel, Software-Selectable,
True Bipolar Input, 12-Bit Plus Sign ADC
AD7327
FEATURES
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V
500 kSPS throughput rate
Eight analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 17 mW
Temperature indicator
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
20-lead TSSOP package
iCMOSprocess technology
GENERAL DESCRIPTION
The AD73271 is an 8-channel, 12-bit plus sign successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power
consumption, and reduced package size.
The AD7327 can accept true bipolar analog input signals. The
AD7327 has four software-selectable input ranges, ±10 V, ±5 V,
±2.5 V, and 0 V to +10 V. Each analog input channel can be
independently programmed to one of the four input ranges.
The analog input channels on the AD7327 can be programmed
to be single-ended, true differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The AD7327 also
allows for external reference operation. If a 3 V reference is
applied to the REFIN/OUT pin, the AD7327 can accept a true
bipolar ±12 V analog input. Minimum ±12 V VDD and VSS
supplies are required for the ±12 V input range. The ADC has a
high speed serial interface that can operate at throughput rates
up to 500 kSPS.
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN/OUT VCC
AD7327
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
I/P
MUX
2.5V
VREF
T/H
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
TEMPERATURE
INDICATOR
CHANNEL
SEQUENCER
CONTROL LOGIC
AND REGISTERS
AGND
VSS DGND
Figure 1.
DOUT
SCLK
CS
DIN
VDRIVE
PRODUCT HIGHLIGHTS
1. The AD7327 can accept true bipolar analog input signals,
±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.
2. The eight analog inputs can be configured as eight single-
ended inputs, four true differential inputs, four pseudo
differential inputs, or seven pseudo differential inputs.
3. 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-
compatible interface.
4. Low power, 17 mW, at a maximum throughput rate of
500 kSPS.
5. Channel sequencer.
Table 1. Similar Devices
Device Throughput
Number Rate
AD7329 1000 kSPS
AD7328 1000 kSPS
AD7324 1000 kSPS
AD7323 500 kSPS
AD7322 1000 kSPS
AD7321 500 kSPS
Number of bits
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
Number of
Channels
8
8
4
4
2
2
1 Protected by U.S. Patent No. 6,731,232.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




AD7327 pdf, 반도체, 판매, 대치품
AD7327
Parameter1
DC ACCURACY4
Resolution
No Missing Codes
Integral Nonlinearity2
B Version
Min Typ Max
13
12-bit
plus sign
11-bit
plus sign
±1.1
±1
Unit
Bits
Bits
Bits
LSB
LSB
−0.7/+1.2
LSB
Differential Nonlinearity2
−0.9/+1.2 LSB
±0.9 LSB
−0.7/+1
LSB
Offset Error2, 5
Offset Error Match2, 5
Gain Error2, 5
Gain Error Match2, 5
Positive Full-Scale Error2, 6
Positive Full-Scale Error Match2, 6
Bipolar Zero Error2, 6
Bipolar Zero Error Match2, 6
Negative Full-Scale Error2, 6
Negative Full-Scale Error Match2,6
−4/+9
−7/+10
±0.6
±0.5
±8
±14
±0.5
±0.5
±4
±7
±0.5
±0.5
±8.5
±7.5
±0.5
±0.5
±4
±6
±0.5
±0.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Test Conditions/Comments
Differential mode
Single-ended/pseudo differential mode
Differential mode; VCC = 3 V to 5.25 V, typ for VCC = 2.7 V
Single-ended/pseudo differential mode, VCC = 3 V to
5.25 V, typ for VCC = 2.7 V
Single-ended/pseudo differential mode
(LSB = FSR/8192)
Differential mode; guaranteed no missing codes to
13 bits
Single-ended mode; guaranteed no missing codes to
12 bits
Single-ended/psuedo differential mode
(LSB = FSR/8192)
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Rev. 0 | Page 4 of 36

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AD7327 전자부품, 판매, 대치품
AD7327
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted.1
Table 3.
Parameter
fSCLK
tCONVERT
tQUIET
t1
t2 2
t3
t4
t5
t6
t7
t8
t9
t10
tPOWER-UP
Limit at TMIN, TMAX
VCC < 4.75 V
50
VCC = 4.75 V to 5.25 V
50
10 10
16 × tSCLK
75
16 × tSCLK
60
12 5
25 20
45 35
26 14
57 43
0.4 × tSCLK
0.4 × tSCLK
13
0.4 × tSCLK
0.4 × tSCLK
8
40 22
10 9
44
22
750 750
500 500
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
25 25
μs typ
Description
VDRIVE ≤ VCC
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal
reference
Power-up from full shutdown/autoshutdown mode, external
reference
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.
CS
SCLK
tCONVERT
t2 t6
12345
3 IDENTIFICATION BITS
t3
DOUT
ADD1 ADD0 SIGN
THREE-
STATE
ADD2
t9
t4 t7
DB11 DB10
t10
DIN
WRITE
REG
SEL1
REG
SEL2
MSB
t1
13 14
t5
DB2 DB1
15
DB0
16
t8
tQUIET
THREE-STATE
LSB
DON’T
CARE
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 7 of 36

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