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PDF ADV7344 Data sheet ( Hoja de datos )
| Número de pieza | ADV7344 | |
| Descripción | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs | |
| Fabricantes | Analog Devices | |
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Data Sheet
Multiformat Video Encoder Six 14-Bit
Noise Shaped Video DACs
ADV7344
FEATURES
74.25 MHz 20-/30-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
6 Noise Shaped Video® (NSV) 14-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 YCrCb (ED and HD)
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
Serial MPU interface with I2C compatibility
3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006-2012 Analog Devices, Inc. All rights reserved.
1 page  
ADV7344
REVISION HISTORY
2/12—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Moved Revision History Section .................................................... 4
Changes to Table 1............................................................................ 5
Changes to Digital Input/Output Specifications—
1.8 V Section ..................................................................................... 8
Changes to Table 21........................................................................ 34
Changes to Table 24........................................................................ 37
Changes to Table 29........................................................................ 42
Changes to 24-/30-Bit 4:4:4 RGB Mode Section ........................ 50
Deleted ED/HD Nonstandard Timing Mode Section, Figure 58,
and Table 42, Renumbered Sequentially ..................................... 54
Added External Sync Polarity Section ......................................... 57
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section .................................................................................... 58
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode Section,
and Figure 59................................................................................... 55
Deleted Figure 60............................................................................ 56
Changes to ED/HD Test Patterns Section ................................... 87
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1.......................................................................... 5
Changes to Table 6............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Table 9.................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions ......................................................................... 10
Added Power Specifications Section, Default Conditions ........ 10
Added Video Performance Specifications, Default
Conditions ....................................................................................... 11
Changes to Table 13........................................................................ 19
Changes to Table 15........................................................................ 20
Changes to MPU Port Description Section ................................ 27
Changes to I2C Operation Section ............................................... 27
Added Table 16 ............................................................................... 27
Data Sheet
Changes to Table 17 ....................................................................... 29
Changes to Table 18 ....................................................................... 30
Changes to Table 21, 0x30 Bit Description ................................. 33
Changes to Table 22, 0x31, Bit Description ................................ 34
Changes to Table 23 ....................................................................... 35
Changes to Table 29 ....................................................................... 40
Changes to Table 30 ....................................................................... 41
Changes to Table 31 ....................................................................... 43
Changes to Table 32 ....................................................................... 45
Added Table 33 ............................................................................... 45
Added Table 34 ............................................................................... 46
Changes to Standard Definition Only Section ........................... 47
Added Figure 52 ............................................................................. 49
Changes to Figure 56...................................................................... 50
Renamed Features Section to Design Features Section............. 52
Changes to ED/HD Nonstandard Timing Mode Section......... 52
Added HD Interlace External P_HSYNC and P_VSYNC
Considerations Section .................................................................. 53
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section .................................................. 53
Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 55
Changes to Programming the FSC Section................................... 55
Changes to Subaddress 0x82, Bit 4 Section................................. 55
Added SD Manual CSC Matrix Adjust Feature Section............ 58
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 59
Changes to SD Brightness Detect Section................................... 60
Changes to Figure 70...................................................................... 62
Added Sleep Mode Section ........................................................... 69
Changes to Pixel and Control Port Readback Section .............. 69
Added SD Teletext Insertion Section........................................... 69
Added Unused Pins Section.......................................................... 71
Added Figure 85 and Figure 86 .................................................... 71
Changes to Power Supply Sequencing Section........................... 73
Changes to Figure 93...................................................................... 76
Changes to SD Wide Screen Signaling Section .......................... 78
Changes to Internal Test Pattern Generation Section ............... 80
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section.................................. 81
Added Configuration Scripts Section.......................................... 93
10/06—Revision 0: Initial Version
Rev. B | Page 4 of 108
5 Page 
ADV7344
Data Sheet
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 9.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134
Control Output Hold Time, t144
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (4×)
Conditions1
Min
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
1.4
1.9
1.9
1.6
1.4
1.5
1.5
1.3
1.4
1.2
1.0
1.4
1.0
1.0
4.0
5.0
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
ED oversampling disabled
ED oversampling enabled
HD oversampling disabled
HD oversampling enabled
Typ
68
67
78
84
41
46
40
44
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: C[9:0], Y[9:0], and S[9:0].
3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4 Guaranteed by characterization.
5 Guaranteed by design.
Max
13
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Rev. B | Page 10 of 108
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV7344.PDF ] | |
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