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NIS5102 데이터시트 PDF




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부품번호 NIS5102 기능
기능 High Side SMART HotPlug IC/Inrush Limiter/Circuit Breaker
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NIS5102 데이터시트, 핀배열, 회로
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NIS5102
High Side
SMART HotPlugE IC/Inrush
Limiter/Circuit Breaker
The NIS5102 is a controller/FET IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed for +12 V applications.
This chip includes a time delay for sequencing applications. It has a
dual function OVLO pin that allows multiple units to be ganged
together for simultaneous turn−on and shutdown, allowing units to be
operated in parallel. It allows for user selectable undervoltage and
overvoltage lockout levels. Its unique current limit circuit allows for
adjustable current limit levels with no external power resistor. An
internal temperature limiting circuit greatly increases the reliability of
this device.
Features
Integrated Power Device
Power Device Thermally Protected
No External Current Shunt Required
Simultaneous Shutdown and Startup for Parallel Operation
Enable/Timer Pin
Power Good
9.0 to 18 V Input Range
10 mW
Main/Mirror MOSFET Current Ratio 1000:1
Pb−Free Packages are Available
Typical Applications
High Availability Systems
Electronic Circuit Breaker
12 V Distributed Architecture
http://onsemi.com
ÎÎÎÎ
MARKING
DIAGRAM
1
5102QPxH
AWLYWWG
9x9 MM, 12 PIN PLLP
CASE 488AB
x = 1 or 2
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free
PIN CONNECTIONS
12 1
11 2
10 13 3
94
85
76
(Bottom View)
ORDERING INFORMATION
Device
Package
Shipping
NIS5102QP1HT1 9x9 mm 1500/Tape & Reel
(Latchoff)
12 Pin PLLP
NIS5102QP1HT1G 12 Pin PLLP 1500/Tape & Reel
(Latchoff)
(Pb−Free)
NIS5102QP2HT1 9x9 mm 1500/Tape & Reel
(Auto−Retry)
12 Pin PLLP
NIS5102QP2HT1G 12 Pin PLLP 1500/Tape & Reel
(Auto−Retry)
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 5
1
Publication Order Number:
NIS5102/D




NIS5102 pdf, 반도체, 판매, 대치품
NIS5102
ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V, RLIMIT = 36 W, CCharge = 100 pF, TJ = 25°C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
CURRENT LIMIT
Current Limit (Short Circuit, RLIMIT = 36 W)
Current Limit (Overload, RLIMIT = 36 W) (Note 3)
ENABLE/TIMER
ILIM1
ILIM2
3.8 4.8 5.8
7.0 7.8 8.6
A
A
Enable Voltage (Turn−On)
Enable Voltage (Turn−Off)
Charging Current (Into External Capacitor)
Turn−on Delay (Time from Enable High to Isource = 100 mA)
CHARGE PUMP
VENon
2.2
VENoff
− 1.6
ICharge 65 77 88
tdelay
− 2.2 −
V
V
mA
ms
CCharge (Voltage on Pin 5 with Respect to Ground)
VCC = 18 Vdc
POWER GOOD
VCcharge
18
− 26 −
V
V
Power Good High Z Signal when FET is Fully Enhanced
− −−− −
Low Z State Output Voltage (ISink = 2 mA)
Vpin7
230 300
mV
Leakage Current (Vpin7 = 12 V, High Z State)
ILeak
− 2.0 10 mA
Power Good Delay
tpwrgood
15
ms
(Time from Power FET is Fully Enhanced to Power Good FET Changing State)
TOTAL DEVICE
Bias Current (Operational, VCC = 12 V)
Bias Current (Non−operational, VCC = 7 V))
Minimum Operating Voltage
IBias
− 1.3 2.0 mA
IBias
− 400 700 mA
Vccmin − 8.5 9.0 V
Output Current
Source Voltage
Enable/Timer
Threshold
Input
Figure 2. Timing Diagram for External Enabled Delay
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NIS5102 전자부품, 판매, 대치품
NIS5102
TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS (continued)
(TA = 25°C unless otherwise noted)
InnppuuttVVooltlatgaege
PPoowwereGr oGoodod
Ouuttppuut tVVooltaltgaege
Ouuttppuut tCCuurrrernetnt
DevviicceeRReeaacchhinigng
Thheerrmmaal lLLimimit it
Figure 12. Turn−On Waveforms for Shorted Output,
Auto−Retry Device
IInnppuuttVVooltlatgaege
OOuuttppuut tCCuurrrernetnt
OOvveerrvoollttaaggee
cCoonnddiitioonn
OutOpuuttpuVtoVltoaltgaege
Power GPooowder Good
Figure 13. Device Response During an Overvoltage
Condition
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