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부품번호 | NUP4201DR2 기능 |
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기능 | Low Capacitance Surface Mount TVS | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 8 페이지수
www.DataSheet4U.com
NUP4201DR2
Low Capacitance Surface
Mount TVS for High−Speed
Data Interfaces
The NUP4201DR2 transient voltage suppressor is designed to
protect equipment attached to high speed communication lines from
ESD, EFT, and lightning.
Features:
• SO−8 Package
• Peak Power − 500 Watts 8 x 20 mS
• ESD Rating:
IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact)
IEC 61000−4−4 (EFT) 40 A (5/50 ns)
IEC 61000−4−5 (lightning) 23 (8/20 ms)
• UL Flammability Rating of 94V−0
Typical Applications:
• High Speed Communication Line Protection
• USB Power and Data Line Protection
• Video Line Protection
• Base Stations
• HDSL, IDSL Secondary IC Side Protection
• Microcontroller Input Protection
MAXIMUM RATINGS
Rating
Symbol Value Unit
Peak Power Dissipation
8 x 20 mS @ TA = 25°C (Note 1)
Junction and Storage
Temperature Range
Ppk 500
TJ, Tstg
−55 to
+150
W
°C
Lead Solder Temperature −
Maximum 10 Seconds Duration
TL 260 °C
1. Non−repetitive current pulse 8 x 20 mS exponential decay waveform
http://onsemi.com
SO−8 LOW CAPACITANCE
VOLTAGE SUPPRESSOR
500 WATTS PEAK POWER
6 VOLTS
PIN CONFIGURATION
AND SCHEMATIC
I/O 1 1
REF 1 2
REF 1 3
I/O 2 4
8 REF 2
7 I/O 4
6 I/O 3
5 REF 2
8
1
SO−8
CASE 751
PLASTIC
MARKING DIAGRAM
P4201
LYW
P4201 = Device Code
L = Location Code
Y = Year
W = Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NUP4201DR2 SO−8
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 3
1
Publication Order Number:
NUP4201DR2/D
NUP4201DR2
APPLICATIONS INFORMATION
The new NUP4201DR2 device is a low capacitance TVS
Diode array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD conditions or
transient voltage conditions. Because of its low capacitance
array configuration, it can be used in high speed I/O data
lines.
The integrated design of the NUP4201DR2 device offers
surge rated, low capacitance steering diodes and a TVS
diode integrated in a single package (SO−8). If a transient
condition occurs, the steering diodes will drive the transient
condition to the positive polarity of the power supply or to
ground. The TVS device protects the power line against
over−voltage conditions to avoid damage in any
downstream components.
NUP4201DR2 Device’s Configurations Options
The NUP4201DR2 is able to protect up to four data lines
against transient over−voltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vcc+Vf). The
diodes will drive the transient current away from the
sensitive circuit.
Data lines are connected at pins 1,4,6 and 7. The negative
reference is connected at pins 5 and 8. These pins must be
connected directly to ground by using a ground plane to
minimize the PCB’s ground inductance. It is very important
to reduce as much as possible the PCB trace lengths to
minimize parasitic inductances.
Option 1
Four Data lines protection and power supply protection
using Vcc as reference.
Option 2
Four Data lines protection with Bias and power supply
isolation resistor.
I/O 1
I/O 2
VCC
10 K
1
2
8
7
36
45
I/O 3
I/O 4
The NUP4201DR2 device can be isolated from the power
supply by connecting a series resistor between pins 2 & 3 and
Vcc. A resistor of 10KW is recommended for isolation
purposes. The internal TVS and steering diodes remain
biased, which provides the advantage of lower capacitance.
Option 3
Four Data lines protection using internal TVS diode as
reference.
I/O 1
I/O 2
1
NC 2
NC 3
4
8
7
6
5
I/O 1
I/O 2
VCC
I/O 3
I/O 4
1
2
3
4
8
7
6
5
I/O 3
I/O 4
In the case of applications in which a positive supply
reference is not available or full isolation is required, the
internal TVS could be used as the reference, so for this
purpose, the pins 2 and 3 are not connected. In this case, the
steering diodes will conduct whenever the voltage on the
protected line exceeds the working voltage of the TVS plus
one diode drop (Vc=Vf + VTVS).
For this configuration, connect pins 2 & 3 directly to the
positive supply rail (Vcc), the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over−voltage on the supply rail.
http://onsemi.com
4
4페이지 NUP4201DR2
−X−
A
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE AB
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45 _
0.10 (0.004)
M
0.25 (0.010) M Z Y S X S
J
SOLDERING FOOTPRINT*
7.0
0.275
1.52
0.060
4.0
0.155
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC
0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.6
0.024
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
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