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PDF NUS2401SNT1 Data sheet ( Hoja de datos )
| Número de pieza | NUS2401SNT1 | |
| Descripción | Integrated PNP/NPN Digital Transistors Array | |
| Fabricantes | ON Semiconductor | |
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NUS2401SNT1
Integrated PNP/NPN Digital
Transistors Array
This new option of integrated digital transistors is designed to
replace a discrete solution array of three transistors and their external
resistor bias network. BRTs (Bias Resistor Transistors) contain a
single transistor with a monolithic bias network consisting of two
resistors; a series base resistor and a base−emitter resistor. The BRT
technology eliminates these individual components by integrating
them into a single device, therefore the integration of three BRTs
results in a significant reduction of both system cost and board space.
This new device is packaged in the SC−74/Case 318F package which
is designed for low power surface mount applications.
Features
• Integrated Design
• Reduces Board Space and Components Count
• Simplifies Circuitry Design
• Offered in Surface Mount Package Technology (SC−74)
• Available in 3000 Unit Tape and Reel
• Pb−Free Package is Available
Typical Applications
• Audio Muting Applications
• Drive Circuits Applications
• Industrial: Small Appliances, Security Systems, Automated Test
• Consumer: TVs and VCRs, Stereo Receivers, CD Players,
Cassette Recorders
MAXIMUM RATINGS (Maximum Ratings are those values beyond which
damage to the device may occur. Electrical Characteristics are not
guaranteed over this range.)
Rating
Symbol
Value
Unit
Collector−Base Voltage
V(BR)CBO
Collector−Emitter Voltage
V(BR)CEO
Emitter−Base Voltage
V(BR)EBO
Collector Current − Continuous
IC
THERMAL CHARACTERISTICS
60
50
7.0
200
Vdc
Vdc
Vdc
mAdc
Characteristic
Symbol
Max
Unit
Power Dissipation
PD 350 mW
Junction Temperature
TJ 150 °C
Storage Temperature
Tstg
−55 to +150
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
http://onsemi.com
(6) (5) (4)
Q3
Q1 Q2
(1) (2) (3)
654
123
SC−74
CASE 318F
STYLE 4
MARKING DIAGRAM
50 M
50 = Specific Device Code
M = Date Code
ORDERING INFORMATION
Device
Package
Shipping†
NUS2401SNT1
SC−74 3000/Tape & Reel
NUS2401SNT1G SC−74 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 2
Publication Order Number:
NUS2401SNT1/D
1 page  
NUS2401SNT1
PACKAGE DIMENSIONS
SC−74
CASE 318F−05
ISSUE K
A
L
65 4
S
12 3
B
D
G
0.05 (0.002)
H
C
M
J
K
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM
LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. 318F−01, −02, −03 OBSOLETE. NEW
STANDARD 318F−04.
INCHES
DIM MIN MAX
A 0.1142 0.1220
B 0.0512 0.0669
C 0.0354 0.0433
D 0.0098 0.0197
G 0.0335 0.0413
H 0.0005 0.0040
J 0.0040 0.0102
K 0.0079 0.0236
L 0.0493 0.0649
M 0 _ 10_
S 0.0985 0.1181
MILLIMETERS
MIN MAX
2.90 3.10
1.30 1.70
0.90 1.10
0.25 0.50
0.85 1.05
0.013 0.100
0.10 0.26
0.20 0.60
1.25 1.65
0 _ 10_
2.50 3.00
STYLE 4:
PIN 1. COLLECTOR 2
2. EMITTER 1/EMITTER 2
3. COLLECTOR 1
4. EMITTER 3
5. BASE 1/BASE 2/COLLECTOR 3
6. BASE 3
SOLDERING FOOTPRINT*
2.4
0.094
1.9
0.074
0.7
0.028
0.95
0.037
0.95
0.037
1.0
0.039
ǒ ǓSCALE 10:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
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