PDF 74AUP1G240 Data sheet ( Hoja de datos )

Número de pieza	74AUP1G240
Descripción	Low-power inverting buffer/line driver
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully speciﬁed for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows ﬂoating input signals. The inputs are disabled when the output enable input OE is HIGH. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s Input-disable feature allows ﬂoating input conditions 1 page NXP Semiconductors 74AUP1G240 Low-power inverting buffer/line driver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ VOH HIGH-level output voltage VOL LOW-level output voltage II input leakage current IOZ OFF-state output current IOFF ∆IOFF ICC power-off leakage current additional power-off leakage current supply current ∆ICC additional supply current CI input capacitance CO output capacitance output enabled output disabled Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V data input; VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V OE input; VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V all inputs; VI = GND to 3.6 V; OE = VCC; VCC = 0.8 V to 3.6 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VCC = 0 V to 3.6 V; VO = GND or VCC VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC − 0.1 - 0.75 × VCC - 1.11 - 1.32 - 2.05 - 1.9 - 2.72 - 2.6 - -- -- -- -- -- -- -- -- -- -- -- -- -- [1] - - [1] - - [2] - - - 0.8 - 1.7 - 1.5 0.70 × VCC - 0.65 × VCC - 1.6 - 2.0 - Max Unit -V -V -V -V -V -V -V -V 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 ±0.1 V V V V V V V V µA µA ±0.2 µA ±0.2 µA 0.5 µA 40 µA 110 µA 1 µA - pF - pF - pF -V -V -V -V 74AUP1G240_1 Product data sheet Rev. 01 — 6 November 2006 © NXP B.V. 2006. All rights reserved. 5 of 19 5 Page NXP Semiconductors 74AUP1G240 Low-power inverting buffer/line driver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter Conditions 25 °C Min Typ[1] Max CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation fi = 1 MHz; capacitance VI = GND to VCC [5] VCC = 0.8 V - 2.7 - VCC = 1.1 V to 1.3 V - 2.9 - VCC = 1.4 V to 1.6 V - 3.0 - VCC = 1.65 V to 1.95 V - 3.2 - VCC = 2.3 V to 2.7 V - 3.7 - VCC = 3.0 V to 3.6 V - 4.2 - [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] ten is the same as tPZH and tPZL [4] tdis is the same as tPHZ and tPLZ [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. −40 °C to +125 °C Unit Min Max Max (85 °C) (125 °C) -- -- -- -- -- -- - pF - pF - pF - pF - pF - pF 12. Waveforms A input VI GND VOH Y output VOL VM t PHL VM t PLH mna640 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (A) to output (Y) propagation delays Table 9. Measurement points Supply voltage Output VCC 0.8 V to 3.6 V VM 0.5 × VCC 74AUP1G240_1 Product data sheet Input VM 0.5 × VCC VI VCC Rev. 01 — 6 November 2006 tr = tf ≤ 3.0 ns © NXP B.V. 2006. All rights reserved. 11 of 19 11 Page

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