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Analog Devices에서 제조한 전자 부품 AD7933은 전자 산업 및 응용 분야에서
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부품번호 AD7933 기능
기능 (AD7933 / AD7934) 12-Bit and 10-Bit Parallel ADCs
제조업체 Analog Devices
로고 Analog Devices 로고


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AD7933 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Preliminary Technical Data
FEATURES
Fast throughput rate: 1.5 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
8 mW max at 1.5 MSPS with 3 V supplies
16 mW max at 1.5 MSPS with 5 V supplies
4 analog input channels with a sequencer
Software configurable analog inputs
4-channel single-ended inputs
2-channel fully differential inputs
2-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
Wide input bandwidth
70 dB SNR at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 1 µA max
28 lead TSSOP package
4-Channel, 1.5 MSPS, 12-Bit and 10-Bit
Parallel ADCs with a Sequencer
AD7933/AD7934
VREFIN/
VREFOUT
VIN0
VIN3
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
AD7933/AD7934
2.5V
VREF
I/P
MUX
T/H
12-/10-BIT
SAR ADC
AND
CONTROL
CLKIN
CONVST
BUSY
SEQUENCER
PARALLEL INTERFACE/CONTROL REGISTER
VDRIVE
DB0 DB11
CS RD WR W/B
Figure 1.
DGND
GENERAL DESCRIPTION
The AD7933/AD7934 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) ADCs. The parts
operate from a single 2.7 V to 5.25 V power supply and feature
throughput rates to 1.5 MSPS. The parts contain a low noise,
wide bandwidth, differential track-and-hold amplifier that can
handle input frequencies up to 20 MHz.
The AD7933/AD7934 feature 4 analog input channels with a
channel sequencer to allow a consecutive sequence of channels
to be converted on. These parts can accept either single-ended,
fully differential, or pseudo-differential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs, which allows for easy interfacing
to microprocessors and DSPs. The input signal is sampled on
the falling edge of CONVST and the conversion is also initiated
at this point.
The AD7933/AD7934 has an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
These parts use advanced design techniques to achieve very low
power dissipation at high throughput rates. They also feature
flexible power management options. An on-chip control register
allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption.
2. Four analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Software configurable analog inputs. Single-ended, pseudo-
differential, or fully differential analog inputs that are
software selectable.
5. Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of VDD.
6. No pipeline delay.
7. Accurate control of the sampling instant via a CONVST
input and once off conversion control.
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD7933 pdf, 반도체, 판매, 대치품
AD7933/AD7934
Preliminary Technical Data
Parameter
VREF Output Impedance
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD7
Normal Mode(Static)
Normal Mode (Operational)
Auto StandBy Mode
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation
Normal Mode (Operational)
Auto Standby Mode (Static)
Auto Shutdown Mode (Static)
Full Shutdown Mode
B Version1
10
15
25
Unit
Ω typ
pF typ
pF typ
Test Conditions/Comments
When in track
When in hold
2.4 V min
0.8 V max
±1
µA max
Typically 10 nA, VIN = 0 V or VDRIVE
10 pF max
2.4 V min
0.4 V max
±10 µA max
10 pF max
Straight (Natural) Binary
Twos Complement
ISOURCE = 200 µA;
ISINK = 200 µA
CODING bit = 0
CODING bit = 1
t2 + 13 tclk + t20
135
1.5
ns
ns max
MSPS max
Full scale step input
2.7/5.25
2.7 /5.25
0.5
3.2
2.6
1.55
90
1
1
1
V min/max
V min/max
mA typ
mA max
mA max
mA typ
µA max
mA typ
µA max
µA max
Digital I/Ps = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 250 kSPS
(Static)
FSAMPLE = 250 kSPS
(Static)
SCLK on or off
16
mW max
VDD = 5 V
8
mW max
VDD = 3 V
450
µW max
VDD = 5 V
270
µW max
VDD = 3 V
5
µW max
VDD = 5 V
3
µW max
VDD = 3 V
5
µW max
VDD = 5 V
3
µW max
VDD = 3 V
1 Temperature range is as follows: B Versions: −40°C to +85°C.
2 See Terminology section.
3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave >3.5 MHz) within the acquisition time may cause an incorrect conversion result to be
returned by the converter.
4 For full common-mode range see
5 Sample tested during initial release to ensure compliance.
6 This device is operational with an external reference in the range 0.1 V to 3.5 V differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.
7 Measured with a midscale dc input.
Rev. PrG | Page 4 of 32

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AD7933 전자부품, 판매, 대치품
Preliminary Technical Data
AD7933/AD7934
TIMING SPECIFICATIONS1
VDD = VDRIVE =2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 3.
Parameter
fCLKIN2
tQUIET
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t133
t144
t15
t16
t17
t18
t19
t20
Limit at TMIN, TMAX
AD7933 AD7934
10 10
24 24
10
10
20
TBD
0
0
25
10
5
0.5 tCLKIN
0
0
55
50
5
40
15
5
10
0
5
TBD
10
10
20
TBD
0
0
25
10
5
0.5 tCLKIN
0
0
55
50
5
40
15
5
10
0
5
TBD
Unit
kHz
min
MHz
max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Description
Minimum time between end of read and start of next conversion, i.e., time from when the
data bus goes into three-state until the next falling edge of CONVST.
CONVST Pulse Width.
CONVST Falling Edge to CLKIN Falling Edge Setup Time.
CLKIN Falling Edge to BUSY Rising Edge.
CS to WR Setup Time.
CS to WR Hold Time.
WR Pulse Width.
Data Setup Time before WR.
Data Hold after WR.
New Data Valid before Falling Edge of BUSY.
CS to RD Setup Time.
CS to RD Hold Time.
RD Pulse Width.
Data Access Time after RD.
Bus Relinquish Time after RD.
Bus Relinquish Time after RD.
HBEN to RD Setup Time.
HBEN to RD Hold Time.
Minimum Time between Reads/Writes.
HBEN to WR Setup Time.
HBEN to WR Hold Time.
CLKIN Falling Edge to BUSY Rising Edge.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance. See Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode
(W/ = 1), Figure 38, Figure 39, and Figure 40.
2 Mark/space ratio for CLKIN is 40/60 to 60/40.
3 The time required for the output to cross TBD.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. PrG | Page 7 of 32

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