AD8117 Datasheet PDF - Analog Devices
| Part Number | AD8117 | |
| Description | Analog Crosspoint Switch | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Data Sheet
FEATURES
High channel count, 32 × 32 high speed, nonblocking switch
array
Differential or single-ended operation
Differential G = +1 (AD8117) or G = +2 (AD8118)
Flexible power supplies
Single +5 V supply, or dual ±2.5 V supplies
Serial or parallel programming of switch array
High impedance output disable allows connection of
multiple devices with minimal loading on output bus
Excellent video performance
>50 MHz 0.1 dB gain flatness
0.05%/0.05° differential gain/phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: 600 MHz
Slew rate: 1800 V/μs
Settling time: 2.5 ns to 1%
Low power of 2.5 W
Low all hostile crosstalk
< −70 dB at 5 MHz
< −43 dB at 600 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
304-ball BGA package (31 mm × 31 mm)
APPLICATIONS
Routing of high speed signals including RGB and component
video routing
KVM
Compressed video (MPEG, wavelet)
Data communications
GENERAL DESCRIPTION
The AD8117/AD8118 are high speed, 32 × 32 analog crosspoint
switch matrices. They offer 600 MHz bandwidth and slew rate of
1800 V/μs for high resolution computer graphics (RGB) signal
switching. With less than −70 dB of crosstalk and −80 dB
isolation (at 5 MHz), the AD8117/AD8118 are useful in many
high speed applications. The 0.1 dB flatness greater than
50 MHz makes the AD8117/AD8118 ideal for composite video
switching.
The AD8117/AD8118 include 32 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off-channels present minimal loading
to an output bus. The AD8117 has a differential gain of +1,
while the AD8118 has a differential gain of +2 for ease of use in
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
600 MHz, 32 × 32 Buffered,
Analog Crosspoint Switch
AD8117/AD8118
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 VDD DGND
AD8117/
AD8118
SER/PAR
WE
CLK
DATA IN
UPDATE
RESET
1
0
192-BIT SHIFT REGISTER
WITH 6-BIT
PARALLEL LOADING
192
PARALLEL LATCH
192
DECODE
32
32 × 6:32 DECODERS
INPUT
RECEIVER
G = +1*
G = +2**
2
1024
OUTPUT
BUFFER
G = +1
2
A0
A1
A2
A3
A4
DATA
OUT
SWITCH
MATRIX
*AD8117 ONLY
**AD8118 ONLY
VPOS VNEG
Figure 1.
VOCM
back terminated load applications. They operate as fully
differential devices or can be configured for single-ended
operation. Either a single +5 V supply or dual ±2.5 V supplies
can be used, while consuming only 500 mA of idle current with
all outputs enabled. The channel switching is performed via a
double-buffered, serial digital control (which can accommodate
daisy chaining of several devices), or via a parallel control,
allowing updating of an individual output without reprogram-
ming the entire array.
The AD8117/AD8118 are packaged in a 304-ball BGA package
and are available over the extended industrial temperature
range of −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
AD8117/AD8118
TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
RESET Pulse Width
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
t7
Limit
Min Typ Max Unit
40 ns
50 ns
50 ns
150 ns
10 ns
90 ns
120 ns
100 ns
60 ns
200 ns
1
WE
0
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t2
t1 t3
OUT31 (D5)
t7
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT30 (D4)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t6
Table 3. Logic Levels
VIH
RESET,
SER/PAR, CLK,
DATA IN,
UPDATE
VIL
RESET,
SER/PAR, CLK,
DATA IN,
UPDATE
2.0 V min
0.6 V max
1 See Figure 15.
Figure 2. Timing Diagram, Serial Mode
VOH
DATA OUT
VOL
DATA OUT
VDD − 0.3 V min DGND + 0.5 V max
IIH
RESET1,
SER/PAR, CLK,
DATA IN,
UPDATE
1 μA max
IIL
RESET1,
SER/PAR, CLK,
DATA IN,
UPDATE
–1 μA min
IOH
DATA OUT
−1 mA max
IOL
DATA OUT
1 mA min
Rev. B | Page 5 of 36
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AD8117 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Product Image and Detail view |  1. - Buffered Analog Crosspoint Switch [ Learn More ] | |
| Download | [ AD8117.PDF Datasheet ] | |
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