Datasheet.kr   

AD9228 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9228은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD9228 자료 제공

부품번호 AD9228 기능
기능 Serial LVDS 1.8 V A/D Converter
제조업체 Analog Devices
로고 Analog Devices 로고


AD9228 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

AD9228 데이터시트, 핀배열, 회로
Data Sheet
Quad, 12-Bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9228
FEATURES
4 ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 82 dBc (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 65 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VREF
SENSE
REFT
REFB
AD9228
12
PIPELINE
ADC
SERIAL
LVDS
12
PIPELINE
SERIAL
ADC
LVDS
12
PIPELINE
ADC
SERIAL
LVDS
12
PIPELINE
SERIAL
ADC
LVDS
REF
SELECT
+– 0.5V
SERIAL PORT
INTERFACE
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
FCO+
FCO–
DCO+
DCO–
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
Figure 1.
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-
channel power-down is supported and typically consumes less
than 2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 119 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.




AD9228 pdf, 반도체, 판매, 대치품
Data Sheet
REVISION HISTORY
12/11—Rev. D to Rev. E
Changes to Output Signals Section and Figure 71......................37
Change to Default Operation and Jumper Selection Settings
Section ..............................................................................................38
Change to Figure 74 ........................................................................41
Added Endnote 3 in Ordering Guide ...........................................53
4/10—Rev. C to Rev. D
Changes to Table 16 ........................................................................35
Updated Outline Dimensions........................................................53
Changes to Ordering Guide...........................................................53
12/09—Rev. B to Rev. C
Updated Outline Dimensions........................................................53
Changes to Ordering Guide...........................................................54
7/07—Rev. A to Rev. B
Changes to Figure 3...........................................................................7
Change to Table 7 ............................................................................10
5/07—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Change to Effective Number of Bits (ENOB)................................4
Changes to Logic Output (SDIO/ODM) Section..........................5
Added Endnote 3 to Table 3.............................................................5
Changes to Pipeline Latency............................................................6
Added Endnote 2 to Table 4.............................................................6
Changes to Figure 2 to Figure 4.......................................................7
Changes to Figure 10 ......................................................................12
Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and
Figure 39 ......................................................................................14
AD9228
Changes to Figure 23 to Figure 26 Captions ...............................15
Change to Figure 35 Caption.........................................................17
Added Figure 46 and Figure 47 .....................................................20
Changes to Figure 51 ......................................................................21
Changes to Clock Duty Cycle Considerations Section ..............22
Changes to Power Dissipation and Power-Down Mode Section ...23
Changes to Figure 61 to Figure 63 Captions ...............................25
Changes to Table 9 Endnote ..........................................................26
Changes to Digital Outputs and Timing Section........................27
Added Table 10 ................................................................................27
Changes to RBIAS Pin Section......................................................28
Deleted Figure 62 and Figure 63 ...................................................27
Changes to Figure 67 ......................................................................29
Changes to Hardware Interface Section.......................................30
Added Figure 68 ..............................................................................31
Changes to Table 15 ........................................................................31
Changes to Reading the Memory Map Table Section ................32
Change to Input Signals Section ...................................................36
Changes to Output Signals Section...............................................36
Changes to Figure 71 ......................................................................36
Changes to Default Operation and
Jumper Selection Settings Section ...........................................37
Changes to Alternative Analog Input
Drive Configuration Section ....................................................38
Changes to Figure 74 ......................................................................40
Changes to Table 17 ........................................................................48
Changes to Ordering Guide...........................................................52
4/06—Revision 0: Initial Version
Rev. E | Page 3 of 56

4페이지










AD9228 전자부품, 판매, 대치품
AD9228
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature Min
AD9228-40
Typ Max
AD9228-65
Min Typ Max
Unit
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
Full 250 250 mV p-p
Full 1.2
1.2 V
25°C 20
20 kΩ
25°C 1.5
1.5 pF
Full 1.2 3.6 1.2 3.6 V
Full 0
0.3
0.3 V
25°C 30
30 kΩ
25°C 0.5
0.5 pF
Full 1.2 3.6 1.2 3.6 V
Full 0
0.3
0.3 V
25°C 70
70 kΩ
25°C 0.5
0.5 pF
Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V
Full 0
0.3 0
0.3 V
25°C 30
30 kΩ
25°C 2
2 pF
Full 1.79
1.79 V
Full 0.05 0.05 V
LVDS
LVDS
Full 247 454 247 454 mV
Full
1.125
1.375
1.125
1.375
V
Offset binary
Offset binary
LVDS
LVDS
Full 150 250 150 250 mV
Full 1.10 1.30 1.10 1.30 V
Offset binary
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
Rev. E | Page 6 of 56

7페이지


구       성 총 30 페이지수
다운로드[ AD9228.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AD9220

Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters

Analog Devices
Analog Devices
AD9221

Monolithic A/D Converters

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵