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AD9237 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9237은 전자 산업 및 응용 분야에서
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부품번호 AD9237 기능
기능 Low Power A/D Converter
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AD9237 데이터시트, 핀배열, 회로
Data Sheet
12-Bit, 20 MSPS/40 MSPS/65 MSPS
3 V Low Power A/D Converter
AD9237
FEATURES
Ultralow power
85 mW at 20 MSPS
135 mW at 40 MSPS
190 mW at 65 MSPS
SNR = 66 dBc to Nyquist at 65 MSPS
SFDR = 80 dBc to Nyquist at 65 MSPS
DNL = ±0.7 LSB
Differential input with 500 MHz bandwidth
Flexible analog input: 1 V p-p to 4 V p-p range
Offset binary, twos complement, or gray code data formats
Output enable pin
2-step power-down
Full power-down and sleep mode
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound and medical imaging
Battery-powered instruments
Hand-held scope meters
Low cost digital oscilloscopes
Low power digital still cameras and copiers
Low power communications
GENERAL DESCRIPTION
The AD9237 is a family of monolithic, single 3 V supply, 12-bit,
20 MSPS/40 MSPS/65 MSPS analog-to-digital converters
(ADC). This family features a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9237 uses a
multistage differential pipelined architecture with output error
correction logic to provide 12-bit accuracy at 20 MSPS/
40 MSPS/65 MSPS data rates and guarantees no missing codes
over the full operating temperature range.
With significant power savings over previously available ADCs,
the AD9237 is suitable for applications in imaging and medical
ultrasound.
Fabricated on an advanced CMOS process, the AD9237 is
available in a 32-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
VIN+
VIN–
REFT
REFB
SHA
MODE2
VREF
SENSE
REF
SELECT
MDAC1
4
A/D
10-STAGE
1 1/2-BIT
PIPELINE
15
A/D
3
CORRECTION LOGIC
12
OUTPUT BUFFERS
AD9237
CLOCK
DUTY CYCLE
STABILIZER
0.5V
MODE
SELECT
OE
OTR
D11
D0
AGND
CLK
PDWN
Figure 1.
MODE
DGND
PRODUCT HIGHLIGHTS
1. Operating at 65 MSPS, the AD9237 consumes a low 190 mW
at 65 MSPS, 135 mW at 40 MSPS, and 85 mW at 20 MSPS.
2. Power scaling reduces the operating power further when
running at lower speeds.
3. The AD9237 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
4. The patented SHA input maintains excellent performance
for input frequencies beyond Nyquist and can be configured
for single-ended or differential operation.
5. The AD9237 is optimized for selectable and flexible input
ranges from 1 V p-p to 4 V p-p.
6. An output enable pin allows for multiplexing of the outputs.
7. Two-step power-down supports a standby mode in addition
to a power-down mode.
8. The OTR output bit indicates when the signal is beyond the
selected input range.
9. The clock duty cycle stabilizer (DCS) maintains converter
performance over a wide range of clock pulse widths.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9237 pdf, 반도체, 판매, 대치품
Data Sheet
AD9237
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, −0.5 dBFS input, 1.0 V internal reference, TMIN to TMAX,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
Reference Input Resistance
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span
VREF = 0.5 V; MODE2 = 0 V
VREF = 1.0 V; MODE2 = 0 V
VREF = 0.5 V; MODE2 = AVDD
VREF = 1.0 V; MODE2 = AVDD
Input Capacitance3
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Power-Down Mode
Standby Power
AD9237BCP-20
Min Typ
Max
12
AD9237BCP-40
Min Typ
Max
12
AD9237BCP-65
Min Typ Max
12
Unit
Bits
12 12 12
Bits
±1.30 ±1.95
±1.30 ±1.95
±1.30 ±1.95 % FSR
±0.70 ±2.10
±0.75 ±2.10
±1.05 ±2.25 % FSR
±0.70 ±0.95
±0.70 ±0.95 −1.00 ±0.70 +1.25 LSB
±0.90 ±1.35
±0.90 ±1.35
±0.90 ±2.00 LSB
±2 ±2
±12 ±12
±2 ppm/°C
±12 ppm/°C
±5 ±25
0.8
±2.5
0.1
7
±5 ±25
0.8
±2.5
0.1
7
±5 ±25
0.8
±2.5
0.1
7
mV
mV
mV
mV
kΩ
1.35 1.35
0.70 0.70
1.35 LSB rms
0.70 LSB rms
1
2
2
4
7
1
2
2
4
7
1 V p-p
2 V p-p
2 V p-p
4 V p-p
7 pF
2.7 3.0
2.25 2.5
3.6
3.6
30.5
3.0
±0.01
85
100 120
1
20
2.7 3.0
2.25 2.5
3.6
3.6
45.5
4.5
±0.01
135
150 180
1
20
2.7 3.0
2.25 2.5
3.6
3.6
64.5
5.5
±0.01
190
210 270
1
20
V
V
mA
mA
% FSR
mW
mW
mW
mW
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
Rev. C | Page 3 of 24

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AD9237 전자부품, 판매, 대치품
AD9237
TIMING DIAGRAM
ANALOG
INPUT
N–1
N
N+1
N+2
N+8
N+3
tA
N+4
N+7
N+5 N+6
CLK
DATA
OUT
N–11 N–10 N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
tPD
Figure 2. Timing Diagram
Data Sheet
Rev. C | Page 6 of 24

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