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PDF PCA8575 Data sheet ( Hoja de datos )
| Número de pieza | PCA8575 | |
| Descripción | Remote 16-bit I/O expander | |
| Fabricantes | NXP Semiconductors | |
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PCA8575
Remote 16-bit I/O expander for I2C-bus with interrupt
Rev. 01 — 30 November 2006
Objective data sheet
1. General description
The PCA8575 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The device consists of a 16-bit quasi-bidirectional port and an I2C-bus interface. The
PCA8575 has a low current consumption and includes latched outputs with high current
drive capability for directly driving LEDs.
The PCA8575 also possesses an interrupt line (INT) which can be connected to the
interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote
I/O can inform the microcontroller if there is incoming data on its ports without having to
communicate via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as
inputs.
2. Features
I 400 kHz I2C-bus interface
I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
I 16-bit remote I/O pins that default to inputs at power-up
I Latched outputs with 25 mA sink capability for directly driving LEDs
I Total package sink capability of 400 mA
I Active LOW open-drain interrupt output
I 8 programmable slave addresses using 3 address pins
I Readable device ID (manufacturer, device type, and revision)
I Low standby current (10 µA max.)
I −40 °C to +85 °C operation
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
I Packages offered: SO24, SSOP24 (QSOP24), TSSOP24, HVQFN24, DHVQFN24
3. Applications
I LED signs and displays
I Servers
I Industrial control
I Medical equipment
I PLCs
I Cellular telephones
1 page  
NXP Semiconductors
PCA8575
Remote 16-bit I/O expander for I2C-bus with interrupt
6.2 Pin description
Table 2.
Symbol
INT
AD1
AD2
P00
P01
P02
P03
P04
P05
P06
P07
VSS
P10
P11
P12
P13
P14
P15
P16
P17
AD0
SCL
SDA
VDD
Pin description
Pin Description
SO24, SSOP24,
HVQFN24
TSSOP24, DHVQFN24
1 22 interrupt output (active LOW)
2 23 address input 1
3 24 address input 2
4 1 quasi-bidirectional I/O 00
5 2 quasi-bidirectional I/O 01
6 3 quasi-bidirectional I/O 02
7 4 quasi-bidirectional I/O 03
8 5 quasi-bidirectional I/O 04
9 6 quasi-bidirectional I/O 05
10 7 quasi-bidirectional I/O 06
11 8 quasi-bidirectional I/O 07
12[1]
9[1] supply ground
13 10 quasi-bidirectional I/O 10
14 11 quasi-bidirectional I/O 11
15 12 quasi-bidirectional I/O 12
16 13 quasi-bidirectional I/O 13
17 14 quasi-bidirectional I/O 14
18 15 quasi-bidirectional I/O 15
19 16 quasi-bidirectional I/O 16
20 17 quasi-bidirectional I/O 17
21 18 address input 0
22 19 serial clock line input
23 20 serial data line input/output
24 21 supply voltage
[1] HVQFN and DHVQFN package die supply ground is connected to both the VSS pin and the exposed center
pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
PCA8575_1
Objective data sheet
Rev. 01 — 30 November 2006
© NXP B.V. 2006. All rights reserved.
5 of 30
5 Page 
NXP Semiconductors
PCA8575
Remote 16-bit I/O expander for I2C-bus with interrupt
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8575 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA8575 registers and I2C-bus/SMBus state machine will initialize to their default
states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)
The PCA8575 provides an open-drain interrupt (INT) which can be fed to a corresponding
input of the microcontroller (see Figure 12, Figure 13, and Figure 14). This gives these
chips a kind of master function which can initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the
signal INT is valid.
The interrupt disappears when data on the port is changed to the original setting or data is
read from or written to the device which has generated the interrupt.
In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the
write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely
deactivated (HIGH).
The interrupt is reset in the read mode on the rising edge of the read from port pulse.
During the resetting of the interrupt itself, any changes on the I/Os may not generate an
interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as
an INT.
VDD
MICROCOMPUTER
INT
device 1
PCA8575
INT
device 2
PCA8575
INT
Fig 14. Application of multiple PCA8575s with interrupt
device 8
PCA8575
INT
002aac676
PCA8575_1
Objective data sheet
Rev. 01 — 30 November 2006
© NXP B.V. 2006. All rights reserved.
11 of 30
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