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SSTU32865 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 SSTU32865은 전자 산업 및 응용 분야에서
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부품번호 SSTU32865 기능
기능 28-bit 1:2 registered buffer
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SSTU32865 데이터시트, 핀배열, 회로
www.DataSheet4U.com
SSTU32865
1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
applications
Rev. 02 — 28 September 2004
Product data sheet
1. General description
The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by
four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is
similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTU32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).
The SSTU32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which—while requiring a minimum
9 mm × 13 mm of board space—allows for adequate signal routing and escape using
conventional card technology.
2. Features
s 28-bit data register supporting DDR2
s Fully compliant to JEDEC standard JESD82-9
s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (i.e. 2 × SSTU32864 or 2 × SSTU32866)
s Parity checking function across 22 input data bits
s Parity out signal
s Controlled output impedance drivers enable optimal signal integrity and speed
s Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
s Supports up to 450 MHz clock frequency of operation
s Optimized pinout for high-density DDR2 module design
s Chip-selects minimize power consumption by gating data outputs from changing state
s Supports Stub Series Terminated Logic SSTL_18 data inputs
s Differential clock (CK and CK) inputs
s Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
s Single 1.8 V supply operation
s Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package




SSTU32865 pdf, 반도체, 판매, 대치품
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
6. Pinning information
6.1 Pinning
ball A1
index area
SSTU32865ET/G
SSTU32865ET
2 4 6 8 10 12
1 3 5 7 9 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
002aab010
Transparent top view
Fig 2. Pin configuration for TFBGA160
9397 750 13799
Product data sheet
Rev. 02 — 28 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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SSTU32865 전자부품, 판매, 대치품
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
Table 2: Pin description …continued
Symbol
Pin
Clock inputs
CK, CK
J1, K1
Type
SSTL_18
Miscellaneous inputs
m.c.l.
U3, V2, V3
m.c.h.
U5, V5
RESET
L1
1.8 V
LVCMOS
VREF
VDDL
VDDR
GND
n.c.
A1, V1
0.9 V
nominal
D4, E4, E6, F4, G4, H4, K4,
K5, N4, N5, P5, P6, R5, R6
E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8
D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9
A2, A4, A5, B3, B4, B5, D6,
D7, V4
Description
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).
Must be connected to a logic LOW
Must be connected to a logic HIGH.
Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.
Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
power supply voltage
power supply voltage
ground
ball present but not connected to die
9397 750 13799
Product data sheet
Rev. 02 — 28 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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