PDF SSTUA32864 Data sheet ( Hoja de datos )

Número de pieza	SSTUA32864
Descripción	configurable registered buffer
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com SSTUA32864 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications Rev. 01 — 12 May 2005 Product data sheet 1. General description The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout conﬁguration of the 1 : 2 pinout from A conﬁguration (when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and un-driven (ﬂoating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must always be held at a valid logic HIGH or LOW level. To ensure deﬁned outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs LOW. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case the setup time requirement for DCS would be the same as for the other Dn data inputs. The SSTUA32864 is available in a 96-ball, low proﬁle ﬁne-pitch ball grid array (LFBGA96) package. 1 page Philips Semiconductors SSTUA32864 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications 123 A DCKE n.c. VREF B D2 DNU GND C D3 D DODT DNU n.c. VDD GND E D5 F D6 DNU DNU VDD GND G n.c. RESET VDD H CK DCS GND J CK K D8 CSR DNU VDD GND L D9 M D10 DNU DNU VDD GND N D11 P D12 DNU DNU VDD GND R D13 T D14 DNU DNU VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 56 QCKEA QCKEB Q2A Q2B Q3A Q3B QODTA QODTB Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB ZOH ZOL Q8A Q8B Q9A Q9B Q10A Q10B Q11A Q11B Q12A Q12B Q13A Q13B Q14A Q14B 002aaa956 Fig 4. Ball mapping; 1 : 2 register A (C0 = 0, C1 = 1); top view 9397 750 14757 Product data sheet 123 A D1 n.c. VREF B D2 DNU GND C D3 D D4 DNU n.c. VDD GND E D5 F D6 DNU DNU VDD GND G n.c. RESET VDD H CK DCS GND J CK K D8 CSR DNU VDD GND L D9 M D10 DNU DNU VDD GND N DODT P D12 DNU DNU VDD GND R D13 T DCKE DNU DNU VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 56 Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB ZOH ZOL Q8A Q8B Q9A Q9B Q10A Q10B QODTA QODTB Q12A Q12B Q13A Q13B QCKEA QCKEB 002aaa957 Fig 5. Ball mapping; 1 : 2 register B (C0 = 1, C1 = 1); top view Rev. 01 — 12 May 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 5 of 19 5 Page Philips Semiconductors SSTUA32864 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications 11. Test information 11.1 Test circuit All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed. The outputs are measured one at a time with one transition per measurement. CK inputs TL = 50 Ω test point RL = 100 Ω DUT CK OUT CK test point (1) CL includes probe and jig capacitance. Fig 6. Load circuit VDD TL = 350 ps, 50 Ω RL = 1000 Ω CL = 30 pF(1) RL = 1000 Ω 002aaa371 LVCMOS RESET VDD/2 tINACT IDD(1) 10 % VDD/2 VDD 0V tACT 90 % 002aaa372 (1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. Fig 7. Voltage and current waveforms; inputs active and inactive times input VICR tW VICR VIH VID VIL 002aaa373 Fig 8. VID = 600 mV VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs. Voltage waveforms; pulse duration 9397 750 14757 Product data sheet Rev. 01 — 12 May 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 11 of 19 11 Page

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