PDF SSTUA32866 Data sheet ( Hoja de datos )

Número de pieza	SSTUA32866
Descripción	configurable registered buffer
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com SSTUA32866 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer with parity for DDR2-667 RDIMM applications Rev. 01 — 15 July 2005 Product data sheet 1. General description The SSTUA32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2 memory modules requiring a parity checking function. It is deﬁned in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is conﬁgurable (using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter conﬁguration can be designated as Register A or Register B on the DIMM. The SSTUA32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is deﬁned as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTUA32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm × 5.5 mm). 2. Features s Conﬁgurable register supporting DDR2 up to 667 MT/s Registered DIMM applications s Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode s Controlled output impedance drivers enable optimal signal integrity and speed s Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) s Supports up to 450 MHz clock frequency of operation s Optimized pinout for high-density DDR2 module design s Chip-selects minimize power consumption by gating data outputs from changing state s Supports SSTL_18 data inputs s Checks parity on the DIMM-independent data inputs s Partial parity output and input allows cascading of two SSTUA32866s for correct parity error processing s Differential clock (CK and CK) inputs s Supports LVCMOS switching levels on the control and RESET inputs s Single 1.8 V supply operation (1.7 V to 2.0 V) s Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package 3. Applications s 400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality 1 page Philips Semiconductors SSTUA32866 1.8 V DDR2-667 conﬁgurable registered buffer with parity 123 A DCKE PPO VREF B D2 DNU GND C D3 DNU D DODT QERR VDD GND E D5 F D6 n.c. VDD n.c. GND G PAR_IN RESET H CK DCS VDD GND J CK K D8 CSR DNU VDD GND L D9 M D10 DNU DNU VDD GND N D11 P D12 DNU DNU VDD GND R D13 T D14 DNU DNU VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 56 QCKEA QCKEB Q2A Q2B Q3A Q3B QODTA QODTB Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB n.c. n.c. Q8A Q8B Q9A Q9B Q10A Q10B Q11A Q11B Q12A Q12B Q13A Q13B Q14A Q14B 002aab109 Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1) 9397 750 14759 Product data sheet 123 A D1 PPO VREF B D2 DNU GND C D3 DNU VDD D D4 QERR GND E D5 F D6 DNU DNU VDD GND G PAR_IN RESET H CK DCS VDD GND J CK K D8 CSR DNU VDD GND L D9 M D10 DNU DNU VDD GND N DODT P D12 DNU DNU VDD GND R D13 T DCKE DNU DNU VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 56 Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB n.c. n.c. Q8A Q8B Q9A Q9B Q10A Q10B QODTA QODTB Q12A Q12B Q13A Q13B QCKEA QCKEB 002aab110 Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1) Rev. 01 — 15 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 5 of 27 5 Page Philips Semiconductors SSTUA32866 1.8 V DDR2-667 conﬁgurable registered buffer with parity Table 6: Symbol IOH IOL Tamb Recommended operating conditions …continued Parameter Conditions HIGH-level output current LOW-level output current ambient temperature operating in free air Min - - 0 Typ Max - −8 -8 - +70 [1] The RESET and Cn inputs of the device must be held at valid levels (not ﬂoating) to ensure proper device operation. [2] The differential inputs must not be ﬂoating, unless RESET is LOW. 10. Characteristics Unit mA mA °C Table 7: Characteristics At recommended operating conditions (see Table 6); unless otherwise speciﬁed. Symbol Parameter Conditions VOH VOL II IDD IDDD Ci HIGH-level output voltage IOH = −6 mA; VDD = 1.7 V LOW-level output voltage IOL = 6 mA; VDD = 1.7 V input current all inputs; VI = VDD or GND; VDD = 2.0 V static standby current RESET = GND; IO = 0 mA; VDD = 2.0 V static operating current RESET = VDD; IO = 0 mA; VDD = 2.0 V; VI = VIH(AC) or VIL(AC) dynamic operating current per MHz, clock only RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V dynamic operating current per MHz, per each data input, 1 : 1 mode RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V dynamic operating current per MHz, per each data input, 1 : 2 mode RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V input capacitance, data and CSR VI = Vref ± 250 mV; VDD = 1.8 V inputs input capacitance, CK and CK inputs input capacitance, RESET input VICR = 0.9 V; Vi(p-p) = 600 mV; VDD = 1.8 V VI = VDD or GND; VDD = 1.8 V Min Typ Max Unit 1.2 - - V - - 0.5 V - - ±5 µA - - 100 µA - - 40 mA - 16 - µA - 11 - µA - 19 - µA 2.5 - 2- 3- 3.5 pF 3 pF 4 pF 9397 750 14759 Product data sheet Rev. 01 — 15 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 11 of 27 11 Page

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