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PDF AD9381 Data sheet ( Hoja de datos )
| Número de pieza | AD9381 | |
| Descripción | HDMI Display Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Internal HDCP keys
HDMI interface
Supports high bandwidth digital content protection
RGB to YCbCr 2-way color conversion
1.8 V/3.3 V power supply
100-lead Pb-free LQFP
RGB and YCbCr output formats
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
(HDCP 1.1)
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9381 offers a high definition multimedia interface
(HDMI) receiver integrated on a single chip. Also included is
support for high bandwidth digital content protection (HDCP)
via an internal key storage.
The AD9381 contains an HDMI 1.0-compatible receiver and
supports all HDTV formats (up to 1080p) and display
resolutions up to SXGA (1280×1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays may now receive
encrypted video content. The AD9381 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
HDMI™ Display Interface
AD9381
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DDCSDA
DDCSCL
SERIAL REGISTER
AND
POWER MANAGEMENT
R/G/B 8 × 3
OR YCbCr
2 DATACK
HDMI RECEIVER
HSYNC
VSYNC
DE
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
DE
S/PDIF
8-CHANNEL
I2S
MCLK
LRCLK
HDCP
HDCP KEYS
AD9381
Figure 1.
Fabricated in an advanced CMOS process, the AD9381 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VD
VDD
DVDD
PVDD
Analog Inputs
Digital Inputs
Digital Output Current
Operating Temperature Range
3.6 V
3.6 V
1.98 V
1.98 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to +85°C
Storage Temperature Range
−65°C to +150°C
Maximum Junction Temperature
150°C
Maximum Case Temperature
150°C
AD9381
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 4.
Level Test
I 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design
and characterization testing.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 44
5 Page 
4:4:4 TO 4:2:2 FILTER
The AD9381 contains a filter that allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.
Input Color Space to Output Color Space
The AD9381 can accept a wide variety of input formats and
either retain that format or convert to another. Input formats
supported are:
• 4:4:4 YCrCb 8-bit
• 4:2:2 YCrCb 8-bit, 10-bit, and 12-bit
• RGB 8-bit
Output modes supported are:
• 4:4:4 YCrCb 8-bit
• 4:2:2 YCrCb 8-bit, 10-bit, and 12-bit
• Dual 4:2:2 YCrCb 8-bit
Color Space Conversion (CSC) Matrix
The CSC matrix in the AD9381 consists of three identical
processing channels. In each channel, three input values are
multiplied by three separate coefficients. Also included are an
offset value for each row of the matrix and a scaling multiple for
all values. Each value has a 13-bit, twos complement resolution
to ensure the signal integrity is maintained. The CSC is
designed to run at speeds up to 150 MHz supporting resolu-
tions up to 1080p at 60 Hz. With any-to-any color space
support, formats such as RGB, YUV, YCbCr, and others are
supported by the CSC.
The main inputs, RIN, GIN, and BIN come from the 8- to 12-bit
inputs from each channel. These inputs are based on the input
format detailed in Table 7. The mapping of these inputs to the
CSC inputs is shown in Table 8.
Table 8. CSC Port Mapping
Input Channel
R/CR
Gr/Y
B/CB
CSC Input Channel
RIN
GIN
BIN
AD9381
One of the three channels is represented in Figure 6. In each
processing channel, the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
–0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_Mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2 .CSC_Mode
The functional diagram for a single channel of the CSC, as
shown in Figure 6, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
a1[12:0]
RIN [11:0]
×
a2[12:0]
×
1
4096
GIN [11:0]
×
a3[12:0]
×
1
4096
+
a4[12:0]
++
CSC_Mode[1:0]
×4 2
ROUT [11:0]
×2 1
0
BIN [11:0]
×
×
1
4096
Figure 6. Single CSC Channel
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings section.
For a detailed functional description and more programming
examples, please refer to the application note AN-795, AD9800
Color Space Converter User's Guide.
Rev. 0 | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9381.PDF ] | |
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