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PDF AD9396 Data sheet ( Hoja de datos )
| Número de pieza | AD9396 | |
| Descripción | Analog/DVI Dual-Display Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Analog/DVI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
150 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
DVI 1.0
150 MHz DVI receiver
Supports HDCP 1.1
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9396 offers designers the flexibility of an analog
interface and digital visual interface (DVI) receiver integrated
on a single chip. Also included is support for high bandwidth
digital content protection (HDCP).
The AD9396 is a complete 8-bit, 150 MSPS monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and 720p) and FPD resolutions up
to SXGA (1280 × 1024 @ 80 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), program-
mable gain, offset, and clamp control. The user provides only
1.8 V and 3.3 V power supply, analog input, and HSYNC.
Three-state CMOS outputs may be powered from 1.8 V to 3.3V.
The on-chip PLL generates a pixel clock from HSYNC. Pixel
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Analog/DVI
Dual-Display Interface
AD9396
FUNCTIONAL BLOCK DIAGRAM
R/G/B OR YPbPrIN0
R/G/B OR YPbPrIN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
ANALOG INTERFACE
2:1
MUX
CLAMP
R/G/B 8 × 3
A/D
OR YCbCr
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
SCL
SDA
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DVI RECEIVER
R/G/B 8 × 3
OR YCbCr
2 DATACK
DE
HSYNC
VSYNC
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
SOGOUT
DE
MCL
MDA
DDCSCL
DDCSDA
HDCP
Figure 1.
AD9396
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9396 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
The AD9396 contains a DVI-compatible receiver and supports
all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 80 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays may now receive
encrypted video content. The AD9396 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9396 is pro-
vided in a space-saving, 100-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0ºC to 70ºC temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9396
Parameter
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
DVDD Supply Voltage
PVDD Supply Voltage
IVD Supply Current (Typical Pattern)1
IVDD Supply Current (Typical Pattern)2
IDVDD Supply Current (Typical Pattern)1, 4
IPVDD Supply Current (Typical Pattern)1
Power-Down Supply Current (IPD)
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew
(TDPS)
Channel-to-Channel Differential Input
Skew (TCCS)
Low-to-High Transition Time for Data and
Controls (DLHT)
Test
Level
IV
IV
IV
IV
V
V
V
V
VI
IV
IV
IV
IV
Low-to-High Transition Time for
DATACK (DLHT)
IV
IV
High-to-Low Transition Time for Data and
Controls (DHLT)
IV
IV
High-to-Low Transition Time for
DATACK (DHLT)
IV
IV
Clock to Data Skew5 (TSKEW)
Duty Cycle, DATACK5
DATACK Frequency (FCIP)
IV
IV
VI
Conditions
AD9396KSTZ-100 AD9396KSTZ-150
Min Typ Max Min Typ Max Unit
3.15 3.3 3.47 3.15 3.3 3.47 V
1.7 3.3 347 1.7 3.3 347 V
1.7 1.8 1.9 1.7 1.8 1.9 V
1.7 1.8 1.9 1.7 1.8 1.9 V
80 100
80 110 mA
40 1003
55 1753 mA
88 110
110 145 mA
26 35
30 40 mA
130 130 mA
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
–0.5
45
20
+2.0 –0.5
50
360 ps
6 Clock
Period
900 ps
1300 ps
650 ps
1200 ps
850 ps
1250 ps
800 ps
1200 ps
2.0 ns
55 %
150 MHz
1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst-case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
Rev. 0 | Page 5 of 48
5 Page 
AD9396
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9396 is a fully integrated solution for capturing analog
RGB or YUV signals and digitizing them for display on flat
panel monitors, projectors, or PDPs. In addition, the AD9396
has a digital interface for receiving DVI signals and is capable of
decoding HDCP-encrypted signals through connections to an
external EEPROM. The circuit is ideal for providing an
interface for HDTV monitors or as the front end to high
performance video scan converters.
Implemented in a high performance CMOS process, the
interface can capture signals with pixel rates of up to 150 MHz.
The AD9396 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. Included in the output formatting is a
color space converter (CSC), which accommodates any input
color space and can output any color space. All controls are
programmable via a 2-wire serial interface. Full integration of
these sensitive analog functions makes system design straight-
forward and less sensitive to the physical and electrical
environment.
DIGITAL INPUTS
All digital control inputs (HSYNC, VSYNC, I2C) on the
AD9396 operate to 3.3 V CMOS levels. In addition, all digital
inputs except the TMDS (HDMI/DVI) inputs are 5 V tolerant.
(Applying 5 V to them does not cause any damage.) TMDS
inputs (Rx0+/Rx0−, Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−)
must maintain a 100 Ω differential impedance (through proper
PCB layout) from the connector to the input where they are
internally terminated (50 Ω to 3.3 V). If additional ESD
protection is desired, use of a California Micro Devices (CMD)
CM1213 (among others) series low capacitance ESD protection
offers 8 kV of protection to the HDMI TMDS lines.
ANALOG INPUT SIGNAL HANDLING
The AD9396 has six high impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V p-p to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or RCA-type con-
nectors. The AD9396 should be located as close as practical to
the input connector. Signals should be routed via 75 Ω matched
impedance traces to the IC input pins.
At the input pins, the signal should be resistively terminated
(75 Ω to the signal ground return) and capacitively coupled to
the AD9396 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9396
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitizes the pixel during a
long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 HIGH SPEED
SIGNAL CHIP BEAD inductor in the circuit, as shown in
Figure 3, gives good results in most applications.
RGB
INPUT
47nF
75Ω
RAIN
GAIN
BAIN
Figure 3. Analog Input Interface Circuit
HSYNC AND VSYNC INPUTS
The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a prepro-
cessed TTL or CMOS level signal.
The HSYNC input includes a Schmitt trigger buffer for
immunity to noise and signals with long rise times. In typical
PC-based graphic systems, the sync signals are TTL-level
drivers feeding unshielded wires in the monitor cable. As such,
no termination is required.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. However, it is
tolerant of 5 V logic signals.
OUTPUT SIGNAL HANDLING
The digital outputs are designed to operate from 1.8 V to 3.3 V
(VDD).
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADC.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.
Rev. 0 | Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9396.PDF ] | |
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