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PDF AD9461 Data sheet ( Hoja de datos )
| Número de pieza | AD9461 | |
| Descripción | IF Sampling ADC | |
| Fabricantes | Analog Devices | |
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16-Bit, 130 MSPS IF Sampling ADC
AD9461
FEATURES
130 MSPS guaranteed sampling rate
78.7 dBFS SNR/90 dBc SFDR with 10 MHz input
(3.4 V p-p input, 130 MSPS)
77.7 dBFS SNR with 170.3 MHz input
(4.0 V p-p input, 130 MSPS)
77.0 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 130 MSPS)
76.3 dBFS SNR/86 dBc SFDR with 225 MHz input
(3.4 V p-p input, 125 MSPS)
89 dBFS two-tone SFDR with 169 MHz and 170 MHz
(130 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.6 LSB typical
INL = ±5.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
APPLICATIONS
MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9461 operates up to 130 MSPS, providing a superior signal-
to-noise ratio (SNR) for instrumentation, medical imaging, and
radar receivers using baseband (<100 MHz) and IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
AD9461
VIN+
VIN–
BUFFER
T/H
CLK+
CLK–
CLOCK
AND TIMING
MANAGEMENT
16
PIPELINE
ADC
CMOS
OR
LVDS
OUTPUT
STAGING
2
32
2
REF
DFS
DCS MODE
OUTPUT MODE
OR
D15 TO D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9461 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP_EP) specified over the industrial
temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. True 16-bit linearity.
2. High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
3. Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP_EP.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD9461
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Input Resistance
Input Capacitance
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
2.0
−10
3.25
247
1.125
0.2
1.3
1.1
AD9461BSVZ
Typ Max
0.8
200
+10
2
0.2
545
1.375
1.5 1.6
1.4 1.7
2
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
Unit
V
V
μA
μA
pF
V
V
mV
V
V
V
kΩ
pF
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Uncertainty (Jitter, tJ)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9461BSVZ
Min Typ Max
130
1
7.7
3.1
3.1
3.35
2.3 3.6 4.8
13
60
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
fsec rms
Rev. 0 | Page 5 of 28
5 Page 
Pin No.
11
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87
48, 64, 76, 88
67
68
70
71
72
73
74
77
78
79
80
81
82
83
84
85
86
89
90
100
Mnemonic
REFB
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
DCO−
DCO+
D0+ (LSB)
D1+
D2+
D3+
D4+
D5+
D6+
D7+
D8+
D9+
D10+
D11+
D12+
D13+
D14+
D15+ (MSB)
OR+
SFDR
AD9461
Description
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 10) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Data Clock Output—Complement.
Data Clock Output—True.
D0 True Output Bit (CMOS Levels).
D1 True Output Bit.
D2 True Output Bit.
D3 True Output Bit.
D4 True Output Bit.
D5 True Output Bit.
D6 True Output Bit.
D7 True Output Bit.
D8 True Output Bit.
D9 True Output Bit.
D10 True Output Bit.
D11 True Output Bit.
D12 True Output Bit.
D13 True Output Bit.
D14 True Output Bit.
D15 True Output Bit.
Out-of-Range True Output Bit.
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz. For applications with
analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR
performance; power dissipation from AVDD2 decreases by ~40 mW.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD9461.PDF ] | |
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