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AD9481 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9481은 전자 산업 및 응용 분야에서
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부품번호 AD9481 기능
기능 A/D Converter
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AD9481 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
DNL = ±0.35 LSB
INL = ±0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 439 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
De-multiplexed CMOS outputs
Power-down mode
Clock duty cycle stabilizer
APPLICATIONS
Digital oscilloscopes
Instrumentation and measurement
Communications
Point-to-point radios
Digital predistortion loops
GENERAL DESCRIPTION
The AD9481 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.
To minimize system cost and power dissipation, the AD9481
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.
The digital outputs are TTL/CMOS-compatible with an option
of twos complement or binary output format. The output data
bits are provided in an interleaved fashion along with output
clocks that simplifies data capture.
8-Bit, 250 MSPS
3.3 V A/D Converter
AD9481
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE AGND DRGND DRVDD AVDD
VIN+
VIN–
DS+
DS–
CLK+
CLK–
REFERENCE
AD9481
T AND H
8-BIT
ADC
PIPELINE
CORE
8
CLOCK
MGMT
LOGIC
PORT 8
A
D7A TO D0A
PORT 8
B
D7B TO D0B
DCO+
DCO–
PDWN
S1
Figure 1.
The AD9481 is available in a Pb-free, 44-lead, surface-mount
package (TQFP-44) specified over the industrial temperature
range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Superior linearity. A DNL of ±0.35 makes the AD9481
suitable for many instrumentation and measurement
applications
2. Power-down mode. A power-down function may be exercised
to bring total consumption down to 15 mW.
3. De-multiplexed CMOS outputs allow for easy interfacing
with low cost FPGAs and standard logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD9481 pdf, 반도체, 판매, 대치품
AD9481
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 2.
Parameter
CLOCK AND DS INPUTS (CLK+, CLK−, DS+, DS−)
Differential Input
Common-Mode Voltage1
Input Resistance
Input Capacitance
LOGIC INPUTS (PDWN, S1)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
Logic 1 Voltage2
Logic 0 Voltage
Output Coding
Temp Test Level
Full IV
Full VI
Full VI
25°C V
Full IV
Full IV
Full VI
Full VI
25°C V
25°C V
Full VI
Full VI
Full IV
AD9481-250
Min Typ Max Unit
200 mV p-p
1.38 1.5 1.68 V
4.2
5.5 6.0
kΩ
4 pF
2.0 V
0.8 V
±160 µA
10 µA
30 kΩ
4 pF
DRVDD − 0.05
0.05
Twos complement or binary
mV
V
1 The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.
2 Capacitive loading only.
Rev. 0 | Page 4 of 28

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AD9481 전자부품, 판매, 대치품
TIMING DIAGRAM
AD9481
VIN
CLK+
CLK–
N–1 tA
N
N+1
tEH tEL
8 CYCLES
1/fS
N+7
N+9
N+8 N+10
DS+
DS–
tHDS
INTERLEAVED DATA OUT
PORT A
STATIC
D7A TO D0A
PORT B
STATIC
D7B TO D0B
DCO+
DCO–
STATIC
tSDS
INVALID
INVALID
INVALID
tPD
N
tSKA
tCPD
tV
N+1
tSKB
Figure 2. Timing Diagram
Rev. 0 | Page 7 of 28

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