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PDF AD9882A Data sheet ( Hoja de datos )
| Número de pieza | AD9882A | |
| Descripción | Dual Interface | |
| Fabricantes | Analog Devices | |
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FEATURES
Analog interface
140 MSPS maximum conversion rate
Programmable analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 140 MSPS
3.3 V power supply
Full sync processing
Midscale clamping
4:2:2 output format mode
Digital interface
DVI 1.0 compatible interface
112 MHz operation
High skew tolerance of 1 full input clock
Sync detect for hot plugging
Supports high bandwidth digital content protection
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converter
Microdisplays
Digital TV
GENERAL DESCRIPTION
The AD9882A offers designers the flexibility of an analog inter-
face and a digital visual interface (DVI) receiver integrated on a
single chip. Also included is support for high bandwidth digital
content protection (HDCP).
Analog Interface
The AD9882A is a complete, 8-bit, 140 MSPS monolithic
analog interface optimized for capturing RGB graphics signals
from personal computers and workstations. Its 140 MSPS
encode rate capability and full power analog bandwidth of 300
MHz sup-ports resolutions up to SXGA (1280 × 1024 at 75 Hz).
The analog interface includes a 140 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), program-
mable gain, offset, and clamp control. The user provides only a
3.3 V power supply, analog input, and Hsync. Three-state
CMOS outputs can be powered from 2.2 V to 3.3 V.
The AD9882A’s on-chip PLL generates a pixel clock from
Hsync. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is typically 500 ps p-p at 140 MSPS.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Dual Interface for
Flat Panel Displays
AD9882A
RAIN
GAIN
BAIN
SOGIN
HSYNC
FILT
VSYNC
SCL
SDA
A0
RX0+
RX0–
RX1+
RX1–
RX2+
RX2–
RXC+
RXC–
RTERM
DDCSCL
DDCSDA
MCL
MDA
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
AD9882A
REF
REFBYPASS
CLAMP
A/D 8 ROUT
CLAMP
A/D 8 GOUT
CLAMP
A/D 8 BOUT
SYNC
PROCESSING AND
CLOCK
GENERATION
DATACK
HSOUT
VSOUT
SOGOUT
SERIAL REGISTER AND
POWER MANAGEMENT
8 ROUT
8
GOUT
8 BOUT
DATACK
HSOUT
DIGITAL INTERFACE
8
DVI
RECEIVER
8
8
ROUT
GOUT
BOUT
DATACK
DE
CSOUT
SOGOUT
DE
HDCP
HSYNC
VSYNC
Figure 1.
The AD9882A also offers full sync processing for composite
sync and sync-on-green (SOG) applications.
Digital Interface
The AD9882A contains a DVI 1.0 compatible receiver and
supports display resolutions up to SXGA (1280 × 1024 at
60 Hz). The receiver features an intrapair skew tolerance of up
to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9882A allows for authentica-
tion of a video receiver, decryption of encoded data at the
receiver, and renewability of that authentication during trans-
mission, as specified by the HDCP v1.0 protocol. It also has
high tolerance of noncompliant HDCP sources.
Fabricated in an advanced CMOS process, the AD9882A is
provided in a space-saving, 100-lead LQFP surface-mount
plastic package and is specified over the 0°C to 70°C
temperature range. It is available in a Pb-free package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9882A
Parameter
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current (Typical Pattern)1
IDD Supply Current (Typical Pattern)1, 2
IPVD Supply Current (Typical Pattern) 1
Total Supply Current with HDCP
(Typical Pattern) 1, 2
ID Supply Current (Worst-Case Pattern)3
IDD Supply Current
(Worst-Case Pattern) 2, 3
IPVD Supply Current
(Worst-Case Pattern) 3
Total Supply Current with HDCP
(Worst-Case Pattern) 2, 3
Power-Down Supply Current (IPD)
AC SPECIFICATIONS
Intrapair (+ to –) Differential Input
Skew (TDPS)
Channel-to-Channel Differential
Input Skew (TCCS)
Low-to-High Transition Time
for Data (DLHT)
Low-to-High Transition Time
for DATACK (DLHT)
High-to-Low Transition Time
for Data (DHLT)
High-to-Low Transition Time
for DATACK (DHLT)
Clock -to- Data Skew,4 tSKEW
Duty Cycle, DATACK4
DATACK Frequency (FCIP)
Conditions
Output drive = high, CL = 10 pF
Output drive = medium,
CL = 7 pF
Output drive = low, CL = 5 pF
Output drive = high, CL = 10 pF
Output drive = medium,
CL = 7 pF
Output drive = low, CL = 5 pF
Output drive = high, CL = 10 pF
Output drive = medium,
CL = 7 pF
Output drive = low, CL = 5 pF
Output drive = high,
CL = 10 pF
Output drive = medium,
CL = 7 pF
Output drive = low, CL = 5 pF
AD9882AKSTZ
Temp Test Level Min Typ Max Unit
Full IV
Full IV
Full IV
25°C V
25°C V
25°C V
Full IV
25°C V
25°C V
25°C V
Full IV
Full VI
3.15 3.3 3.45 V
2.2 3.3 3.45 V
3.15 3.3 3.45 V
237 mA
25 mA
57 mA
340 367 mA
247 mA
61 mA
57 mA
385 420 mA
30 35 mA
Full IV
Full IV
Full IV
360 ps
1 Clock Period
2.2 ns
Full IV
Full IV
Full IV
2.5 ns
3.2 ns
1.0 ns
Full IV
Full IV
Full IV
1.6 ns
2.1 ns
2.2 ns
Full IV
Full IV
Full IV
1.9 ns
1.7 ns
1.0 ns
Full IV
Full IV
Full IV
Full IV
Full VI
–0.5
40 46
25
1.0 ns
1.4 ns
+2.0 ns
50 %
112 MHz
1 The typical pattern contains a gray scale area. Output drive = high.
2 DATACK load = 10 pF, data load = 10 pF.
3 The worst-case pattern contains a black and white checkerboard pattern. Output drive = high.
4 Drive strength = 11.
Rev. 0 | Page 5 of 40
5 Page 
AD9882A
Table 6. Interface Selection Controls
AIO
(0xF Bit 2)
Analog Interface Digital Interface
Detect
Detect
1X
X
00
0
1
1
X
1
0
1
AIS
(0x0F, Bit 1)
0
1
None
X
Active
Interface
Analog
Digital
Neither interface
was detected.
Digital
X Analog
0 Analog
1 Digital
Description
Force the analog interface active.
Force the digital interface active.
Both interfaces are powered down.
The digital interface was detected. Power
down the analog interface.
The analog interface was detected. Power
down the digital interface.
Both interfaces were detected. The
analog interface gets priority.
Both interfaces were detected. The digital
interface gets priority.
Table 7. Power-Down Modes, 4:2:2 and 4:4:4 Format Descriptions
Mode
Power-
Down1
Analog
Interface
Detect2
Digital Active
Interface Interface
Detect3 Override
Soft Power-Down
(Seek Mode)
1
0
00
Digital Interface On 1
0
10
Analog Interface On 1
4:4:4 Format
Analog Interface On 1
4:2:2 Format
Serial Bus
Arbitrated Interface
Serial Bus
Arbitrated Interface
Serial Bus
Arbitrated Interface
Override to Analog
Interface
Override to Analog
Interface
Override to Digital
Interface
Absolute Power-
Down
1
1
1
1
1
1
0
1
1
1
1
1
1
1
X
X
00
00
11
11
11
X1
X1
11
XX
Active
Interface
Select
X
4:2:2
Formatting
X
XX
X0
X1
00
01
1X
Data Sheet Signals Powered
On
Serial bus, digital interface clock
detect, analog interface clock
detect, SOG
Serial bus; digital interface and
analog interface activity detect;
SOG, band gap reference; red,
green, and blue outputs
Serial bus; analog interface and
digital interface clock detect;
SOG, band gap reference; red,
green, and blue outputs
Serial bus; analog interface and
digital interface clock detect;
SOG, band gap reference; red
and green outputs only
Same as the analog interface in
4:4:4 mode
Same as the analog interface in
4:2:2 mode
Same as digital interface mode
00
01
1X
Same as the analog interface
4:4:4 mode
Same as the analog interface
4:2:2 mode
Same as digital interface mode
XX
Serial bus
1 Power-down is controlled via Bit 1 in Serial Bus Register 0x14.
2 Analog interface detect is determined by OR’ing Bits 7, 6, and 5 in Serial Bus Register 0x15.
3 Digital interface detect is determined by Bit 4 in Serial Bus Register 0x15.
Rev. 0 | Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9882A.PDF ] | |
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