PDF AD9923A Data sheet ( Hoja de datos )

Número de pieza	AD9923A
Descripción	CCD Signal Processor
Fabricantes	Analog Devices
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No Preview Available ! CCD Signal Processor with V-Driver and Precision Timing Generator AD9923A FEATURES Integrated 15-channel V-driver 12-bit, 36 MHz analog-to-digital converter (ADC) Similar register map to the AD9923 5-field, 10-phase vertical clock support Complete on-chip timing generator Precision Timing core with <600 ps resolution Correlated double sampler (CDS) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) Black level clamp with variable level control On-chip 3 V horizontal and RG drivers 2-phase and 4-phase H-clock modes Electronic and mechanical shutter support On-chip driver for external crystal On-chip sync generator with external sync input 8 mm × 8 mm CSP_BGA package with 0.65 mm pitch APPLICATIONS Digital still cameras GENERAL DESCRIPTION The AD9923A is a complete 36 MHz front-end solution for digital still cameras and other CCD imaging applications. Similar to the AD9923 product, the AD9923A includes the analog front end (AFE), a fully programmable timing generator (TG), and a 15-channel vertical driver (V-driver). A Precision Timing™core allows adjustment of high speed clocks with approximately 600 ps resolution at 36 MHz operation. The on-chip V-driver supports up to 15 channels for use with 5-field, 10-phase CCDs. The analog front end includes black level clamping, CDS, VGA, and a 12-bit ADC. The timing generator and V-driver provide all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor gate pulses, substrate clock, and substrate bias control. The internal registers are programmed using a 3-wire serial interface. Packaged in an 8 mm × 8 mm CSP_BGA, the AD9923A is specified over an operating temperature range of −25°C to +85°C. FUNCTIONAL BLOCK DIAGRAM REFT REFB –3dB, 0dB, +3dB, +6dB +6dB TO +42dB CCDIN CDS VGA VREF AD9923A 12-BIT ADC 12 RG HL H1 TO H4 V1, V2, V3, V4, V5A, V5B, V6, V7A, V7B, V8, V9, V10, V11, V12, V13 HORIZONTAL DRIVERS 4 15 V-DRIVER 13 XV1 TO XV13 VERTICAL 8 TIMING CONTROL XSG1 TO XSG8 2 XSUBCK, XSUBCNT 3 INTERNAL CLOCKS CLAMP PRECISION TIMING GENERATOR SYNC GENERATOR INTERNAL REGISTERS SUBCK VSUB, MSHUT, STROBE HD VD SYNC CLI Figure 1. CLO D0 TO D11 DCLK SL SDI SCK Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved. 1 page AD9923A DIGITAL SPECIFICATIONS DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage Conditions/Comments Powered by DVDD, DRVDD At IOH = 2 mA At IOL = 2 mA Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 DVDD − 0.5, DRVDD − 0.5 Typ Max Unit V 0.6 V 10 μA 10 μA 10 pF V 0.5 V H-DRIVER SPECIFICATIONS HVDD = RGVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 3. Parameter RG and H-DRIVER OUTPUTS High Level Output Voltage Low Level Output Voltage Maximum Output Current Maximum Load Capacitance Conditions/Comments RG, HL, and H1 to H4 powered by RGVDD, HVDD At maximum current At maximum current Programmable For each output Min RGVDD − 0.5, HVDD − 0.5 30 100 Typ Max Unit V 0.5 V mA pF VERTICAL DRIVER SPECIFICATIONS VDD1 = VDD2 = 3.3 V, VH1 = VH2 = 15 V, VM1 = VM2 = VMM = 0 V, VL1 = VL2 = VLL = −7.5 V, 25°C. Table 4. Parameter V-DRIVER OUTPUTS Delay Time VL to VM and VM to VH VM to VL and VH to VM Rise Time VL to VM VM to VH Fall Time VM to VL VH to VM Output Currents at −7.25 V at −0.25 V at +0.25 V at +14.75 V RON SUBCK OUTPUT Delay Time VLL to VH VH to VLL VLL to VMM Conditions/Comments Simplified load conditions, 3000 pF to ground Rising edges Falling edges Simplified load conditions, 1000 pF to ground Rev. A \| Page 4 of 84 Symbol Min Typ Max Unit tPLM, tPMH tPML, tPHM tRLM tRMH tFML tFHM 35 35 125 260 220 125 +10 −22 +22 −10 35 ns ns ns ns ns ns mA mA mA mA Ω tPLH 25 ns tPHL 30 ns tPLM 25 ns 5 Page AD9923A Pin No. A8 A9 F11 E11 D11 C11 B11 C10 K6 F5 G5 G6 F1 G1 H3 H2 H1 J3 J2 J1 K3 K2 K1 L3 L2 D2 E2 C8 G10 E7 G9 C4 C5 F10 C6 C7 G11 H11 H10 F6 F7 E10 K11 J5 J7 J8 A11, E6, H9, J6, J9, J10, J11, K4, K7, L1, L6, L9, L11, G2, G3 Mnemonic CLI CLO H1 H2 H3 H4 HL RG VSUB MSHUT STROBE SUBCK DCLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VD HD V1 V2 V3 V4 V5A V5B V6 V7A V7B V8 V9 V10 V11 V12 V13 VDR_EN TEST0 TEST1 TEST3 NC Type 1 DI DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DIO DIO VO3 VO2 VO3 VO2 VO3 VO3 VO2 VO3 VO3 VO2 VO2 VO2 VO3 VO3 VO2 DI DI DI DI Description Reference Clock Input (Master Clock). Clock Output for Crystal. CCD Horizontal Clock 1. CCD Horizontal Clock 2. CCD Horizontal Clock 3. CCD Horizontal Clock 4. CCD Last Horizontal Clock. CCD Reset Gate Clock. CCD Substrate Bias. Mechanical Shutter Pulse. Strobe Pulse. CCD Substrate Clock (E Shutter). Data Clock Output. Data Output (LSB). Data Output. Data Output. Data Output. Data Output. Data Output. Data Output. Data Output. Data Output. Data Output. Data Output. Data Output (MSB). Vertical Sync Pulse. Input in slave mode, output in master mode. Horizontal Sync Pulse. Input in slave mode, output in master mode. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. V-Driver Output Enable pin. Test Input. Must be tied to VSS1 or VSS2. Test Input. Must be tied to VSS1 or VSS2. Test Input. Must be tied to VDD1 or VDD2. No Connect. 1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, DIO = digital input/output, P = power, VO2 = Vertical Driver Output 2 level, VO3 = Vertical Driver Output 3 level. Rev. A \| Page 10 of 84 11 Page

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Número de pieza	Descripción	Fabricantes
AD9923A	CCD Signal Processor	Analog Devices

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