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AD9929 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9929은 전자 산업 및 응용 분야에서
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부품번호 AD9929 기능
기능 CCD Signal Processor
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AD9929 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
36 MSPS correlated double sampler (CDS)
12-bit 36 MHz A/D converter
On-chip vertical driver for CCD image sensor
On-chip horizontal driver for CCD image sensor
6 dB to 40 dB variable gain amplifier (VGA)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 0.58 ns resolution
2-phase H-clock modes
4-phase vertical transfer clocks
Electronic and mechanical shutter modes
On-chip sync generator with external sync option
64-lead, plastic ball, 9 × 9 grid array Pb-free package
APPLICATION
Digital still cameras
Digital video camcorders
CCD Signal Processor with
Precision Timing™ Generator
AD9929
PRODUCT DESCRIPTION
The AD9929 is a highly integrated CCD signal processor for
digital still camera and digital video camera applications. It
includes a complete analog front end with A/D conversion,
combined with a full-function, programmable timing generator.
The AD9929 also includes horizontal and vertical clock drivers,
which allow direct connection to the CCD image sensor.
The AD9929 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, a CDS, a VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor
gate pulses, a substrate clock, and a substrate bias pulse. Oper-
ation is programmed using a 3-wire serial interface.
The AD9929 is packaged in a 64-lead CSPBGA. It is specified
over an operating temperature range of 25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
AD9929
CDS
6dB TO 40dB
VGA
VREF
ADC
12
DOUT
VSUB
RG
H1, H2
V1, V2,
V3, V4
SUBCK
HORIZONTAL
DRIVERS
2
4
VERTICAL
DRIVERS
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
CLAMP
INTERNAL
REGISTERS
DCLK1
FD/DCLK2
MSHUT
STROBE
HD VD SYNC CLI
Figure 1.
SL SCKS DI
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD9929 pdf, 반도체, 판매, 대치품
AD9929
DIGITAL SPECIFICATIONS
Table 2. RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max Unit
LOGIC INPUTS
High Level Input Voltage
VIH 2.1
V
Low Level Input Voltage
VIL 0.6 V
High Level Input Current
IIH 10 µA
Low Level Input Current
IIL 10 µA
Input Capacitance
CIN 10 pF
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ IOH = 2 mA
VOH 2.2
V
Low Level Output Voltage @ IOL = 2 mA
VOL
0.5 V
RG and H-DRIVER OUTPUTS (H1 to H2)
High Level Output Voltage @ Max Current
VOH VDD − 0.5
V
Low Level Output Voltage @ Max Current
VOL
0.5 V
RG Maximum Output Current (Programmable)
15 mA
H1 and H2 Maximum Output Current (Programmable)
30 mA
Maximum Load Capacitance
100 pF
ANALOG SPECIFICATIONS
Table 3. AVDD = 3.0 V, fCLI = 36 MHz, TMIN to TMAX, unless otherwise noted.
Parameter
Min Typ
Max
CDS
Allowable CCD Reset Transient
500
Max Input Range before Saturation
1.0
Max CCD Black Pixel Amplitude
±100
VARIABLE GAIN AMPLIFIER (VGA)
Max Output Range
2.0
Gain Control Resolution
1024
Gain Monotonicity
Guaranteed
Gain Range
Low Gain
6
Max Gain
40
BLACK LEVEL CLAMP
Clamp Level Resolution
255
Clamp Level
Min Clamp Level
0
Max Clamp Level
255
A/D CONVERTER
Resolution
10
Differential Nonlinearity (DNL)
±0.5
No Missing Codes
Guaranteed
Full-Scale Input Voltage
2.0
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
Reference Bottom Voltage (REFB)
1.0
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code = 22)
6
Max Gain (VGA Code = 994)
40
Peak Nonlinearity, 500 mV Input Signal
0.1
Total Output Noise
0.3
Power Supply Rejection (PSR)
40
Unit
mV
V p–p
mV
V p–p
Steps
dB
dB
Steps
LSB
LSB
LSB
Bits
LSB
V
V
V
dB
dB
%
LSB rms
dB
Notes
See input signal characteristics in Table 1.
LSB measured at ADC output.
Includes entire signal chain.
Gain = (0.035 × Code) + 5.2 dB.
12 dB gain applied.
AC grounded input, 6 dB gain applied.
Measured with step change on supply.
Rev. A | Page 4 of 64

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AD9929 전자부품, 판매, 대치품
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width.“No missing codes guaranteed to
12-bit resolution” indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal-chain specification, refers to the
peak deviation of the output of the AD9929 from a true straight
line. The point used as zero scale occurs 1/2 LSB before the first
code transition. “Positive full scale” is defined as a level 1 and
1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always appro-
priately gained up to fill the ADC’s full-scale range.
AD9929
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSBs, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
1 LSB = (ADC full scale/2N codes) when N is the bit resolution
of the ADC. For the AD9929, 1 LSB is 0.5 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Rev. A | Page 7 of 64

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