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PDF AD9985A Data sheet ( Hoja de datos )
| Número de pieza | AD9985A | |
| Descripción | Analog Interface | |
| Fabricantes | Analog Devices | |
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FEATURES
Variable analog input bandwidth control
Variable SOGIN bandwidth control
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Selectable input filtering
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TVs
110 MSPS/140 MSPS
Analog Interface for Flat Panel Displays
AD9985A
RIN
GIN
BIN
HSYNC
COAST
CLAMP
FILT
SOGIN
SCL
SDA
A0
FUNCTIONAL BLOCK DIAGRAM
AUTO-CLAMP
LEVEL ADJUST
CLAMP
8
A/D ROUTA
AUTO-CLAMP
LEVEL ADJUST
CLAMP
A/D
AUTO-CLAMP
LEVEL ADJUST
CLAMP
A/D
8
8
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER AND
POWER MANAGEMENT
REF
AD9985A
GOUTA
BOUTA
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
Figure 1.
GENERAL DESCRIPTION
The AD9985A is a complete 8-bit, 140 MSPS, monolithic
analog interface optimized for capturing RGB graphics signals
from personal computers and workstations. Its 140 MSPS
encode rate capability and full power analog bandwidth of 300
MHz support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and horizontal sync (Hsync) and Coast signals.
Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.
The AD9985A’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the Coast signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or can be provided by the
user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985A is
provided in a space-saving 80-lead LQFP surface-mount
Pb-free plastic package, and is specified over the –40°C to
+85°C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data-to-Clock Skew
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTAH
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle, DATACK
Output Coding
Temp
Test
Level
Min
25°C I
Full VI
25°C I
Full VI
AD9985ABSTZ-110
Typ Max
8
±0.5 +1.25/−1.0
+1.5/−1.0
±0.5 ±1.85
±3.2
Full VI
Full VI
25°C V
25°C IV
Full IV
Full VI
Full VI
Full VI
Full VI
Full V
Full VI
Full IV
Full IV
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full IV
Full VI
Full IV
25°C IV
Full IV
Full IV
Full VI
Full VI
Full V
Full V
25°C V
Full VI
Full VI
Full IV
1.0
46
110
−0.5
4.7
4.0
300
4.7
4.0
250
4.7
15
110
2.5
VD − 0.1
45
100
7
1.5
49
1.25
±100
400
15
3
50
Binary
0.5
1
2
8.0
52
10
+2.0
110
12
7001
10001
0.8
−1.0
1.0
0.1
55
Rev. 0 | Page 5 of 32
AD9985A
Unit
Bits
LSB
LSB
LSB
LSB
V p-p
V p-p
ppm/°C
μA
μA
mV
% FS
% FS
V
ppm/°C
MSPS
MSPS
ns
μs
μs
ns
μs
μs
ns
μs
μs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
μA
μA
pF
V
V
%
5 Page 
AD9985A
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9985A is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel moni-
tors or projectors. The circuit is ideal for providing a computer
interface for HDTV monitors or as the front end to high
performance video scan converters. Implemented in a high
performance CMOS process, the interface can capture signals
with pixel rates up to 110 MHz.
The AD9985A includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less
sensitive to the physical and electrical environment.
With a typical power dissipation of only 500 mW and an
operating temperature range of 0°C to 70°C (−40°C to +85°C
for the AD9985ABST), the device requires no special
environmental considerations.
DIGITAL INPUTS
All digital inputs on the AD9985A operate to 3.3 V CMOS
levels. However, all digital inputs are 5 V tolerant. Applying 5 V
to them does not cause any damage.
INPUT SIGNAL HANDLING
The AD9985A has one high impedance analog input pin for
each of the red, green, and blue channels. They accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or via BNC connectors.
The AD9985A should be located as close as practical to the
input connector. Signals should be routed via matched-
impedance traces (normally 75 Ω) to the IC input pins.
At this point, the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9985A inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
When impedances are perfectly matched, the best performance
can be obtained with the widest possible signal bandwidth. The
ultrawide bandwidth inputs of the AD9985A (300 MHz) can
track the input signal continuously as it moves from one pixel
level to the next, and digitize the pixel during a long, flat pixel
time. In many systems, however, there are mismatches,
reflections, and noise, which can result in excessive ringing and
distortion of the input waveform. This makes it more difficult
to establish a sampling phase that provides good image quality.
It has been shown that a small inductor in series with the input
is effective in rolling off the input bandwidth slightly and
providing a high quality signal over a wider range of conditions.
Using a Fair-Rite #2508051217Z0 High Speed Signal Chip Bead
inductor in the circuit of Figure 3 yields good results in most
applications.
RGB
INPUT
47nF
75Ω
RIN
GIN
BIN
Figure 3. Analog Input Interface Circuit
HSYNC, VSYNC INPUTS
The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a preproc-
essed TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
OUTPUT SIGNAL HANDLING
The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as low
as 2.5 V for compatibility with other 2.5 V logic.
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADCs.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, black is at 300 mV, and white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This
introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9985A.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced that results in the ADCs producing a
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9985A.PDF ] | |
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