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PDF CS91 Data sheet ( Hoja de datos )

Número de pieza CS91
Descripción Standard cell array
Fabricantes Fujitsu Media Devices 
Logotipo Fujitsu Media Devices Logotipo



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FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
Standard cell array
DS06-20208-3E
CS91 Series
DESCRIPTION
The CS91 series 0.11 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16
ps, resulting in both integration and speed about three times higher than conventional products.
FEATURES
• Technology
: 0.11 µm silicon-gate CMOS, 5- to 8-layer wiring (Copper is used as wire material.) ,
Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity)
• Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip.
• Supply voltage : +1.2 V ± 0.1 V (standard specification)
• Junction temperature range : 40 °C to +125 °C
• Gate delay time : tpd = 16 ps (1.2 V, inverter, F/O = 1)
• Gate power consumption : Pd = 6.6 nW/MHz/BC (1.2 V, inverter, F/O = 1)
• Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for
transmission
• Special interfaces* : P-CML, LVDS, PCI, SSTL, HSTL, T-LVTTL, and others.
• Buffer cell dedicated to crystal oscillator
• IP macros*
: CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others.
• Compiled cells (RAM/ROM/multiplier, and others.)
• Uses industry standard tools and supports the optimum tools for the application
• Short-term development using a physical prototyping tool
• Hierarchical design environment for supporting large-scale circuits
• Support for SIGNAL INTEGRITY, EMI noise reduction
• Support for High resolution RC extraction base delay calculation environment
• Support for optimization environment of power supply wire
(Continued)
Copyright©2002-2006 FUJITSU LIMITED All rights reserved

1 page




CS91 pdf
CS91 Series
RECOMMENDED OPERATING CONDITIONS
Single power supply (VDD = 1.2 V ± 0.1 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Junction temperature
Symbol
VDD
VIH
VIL
Tj
Min
1.1
VDD × 0.7
0.3
40
Value
Typ
1.2
(VSS = 0 V)
Max
1.3
VDD + 0.3
VDD × 0.3
+125
Unit
V
V
V
°C
Dual power supply (VDDE = 3.3 V ± 0.3 V, VDDI = 1.2 V ± 0.1 V)
Parameter
Symbol
Power supply voltage
“H” level input voltage
“L” level input voltage
Junction temperature
3.3 V supply voltage
1.2 V supply voltage
3.3 V CMOS level
1.2 V CMOS level
3.3 V CMOS level
1.2 V CMOS level
VDDE
VDDI
VIH
VIL
Tj
Min
3.0
1.1
2.0
VDDI × 0.7
0.3
0.3
40
Value
Typ
3.3
1.2
(VSS = 0 V)
Max
3.6
1.3
VDDE + 0.3
VDDI + 0.3
+0.8
VDDI × 0.3
+125
Unit
V
V
V
V
V
V
°C
Dual power supply (VDDE = 2.5 V ± 0.2 V, VDDI = 1.2 V ± 0.1 V)
Parameter
Symbol
Power supply voltage
“H” level input voltage
“L” level input voltage
Junction temperature
2.5 V supply voltage
1.2 V supply voltage
2.5 V CMOS level
1.2 V CMOS level
2.5 V CMOS level
1.2 V CMOS level
VDDE
VDDI
VIH
VIL
Tj
Min
2.3
1.1
1.7
VDDI × 0.7
0.3
0.3
40
Value
Typ
2.5
1.2
(VSS = 0 V)
Max
2.7
1.3
VDDE + 0.3
VDDI + 0.3
+0.7
VDDI × 0.3
+125
Unit
V
V
V
V
V
V
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
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